📄 lib_at91.s79
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NAME lib_at91
RTMODEL "__code_model", "small"
RTMODEL "__cpu_mode", "arm"
RTMODEL "__data_model", "absolute"
RTMODEL "__endian", "little"
RTMODEL "__rt_version", "2"
RTMODEL "__thumb_aware", "enabled"
RSEG CSTACK:DATA:NOROOT(2)
RSEG HUGE_I:HUGEDATA:SORT:NOROOT(2)
RSEG HUGE_ID:HUGECONST:SORT:NOROOT(2)
PUBWEAK `?*?HUGE_ID`
PUBWEAK ?init?tab?HUGE_I
PUBLIC PIO_DESC
PUBLIC Pio
PUBLIC TC0_DESC
PUBLIC TC1_DESC
PUBLIC TC2_DESC
PUBLIC TCB_DESC
PUBLIC USART0_DESC
PUBLIC USART1_DESC
PUBLIC at91_clock_close
FUNCTION at91_clock_close,0203H
PUBLIC at91_clock_get_status
FUNCTION at91_clock_get_status,0203H
PUBLIC at91_clock_open
FUNCTION at91_clock_open,0203H
PUBLIC at91_clock_set_mode
FUNCTION at91_clock_set_mode,0203H
LOCFRAME CSTACK, 4, STACK
PUBLIC at91_default_fiq_handler
FUNCTION at91_default_fiq_handler,0203H
PUBLIC at91_default_irq_handler
FUNCTION at91_default_irq_handler,0203H
PUBLIC at91_pio_close
FUNCTION at91_pio_close,0203H
PUBLIC at91_pio_open
FUNCTION at91_pio_open,0203H
PUBLIC at91_pio_read
FUNCTION at91_pio_read,0203H
LOCFRAME CSTACK, 20, STACK
PUBLIC at91_pio_set_mode
FUNCTION at91_pio_set_mode,0203H
PUBLIC at91_pio_write
FUNCTION at91_pio_write,0203H
PUBLIC at91_spurious_handler
FUNCTION at91_spurious_handler,0203H
PUBLIC at91_tc_close
FUNCTION at91_tc_close,0203H
LOCFRAME CSTACK, 4, STACK
PUBLIC at91_tc_get_status
FUNCTION at91_tc_get_status,0203H
PUBLIC at91_tc_open
FUNCTION at91_tc_open,0203H
LOCFRAME CSTACK, 24, STACK
PUBLIC at91_tc_read
FUNCTION at91_tc_read,0203H
PUBLIC at91_tc_set_mode
FUNCTION at91_tc_set_mode,0203H
PUBLIC at91_tc_trig_cmd
FUNCTION at91_tc_trig_cmd,0203H
LOCFRAME CSTACK, 4, STACK
PUBLIC at91_tc_write
FUNCTION at91_tc_write,0203H
PUBLIC at91_usart_close
FUNCTION at91_usart_close,0203H
LOCFRAME CSTACK, 12, STACK
PUBLIC at91_usart_get_status
FUNCTION at91_usart_get_status,0203H
PUBLIC at91_usart_open
FUNCTION at91_usart_open,0203H
LOCFRAME CSTACK, 24, STACK
PUBLIC at91_usart_read
FUNCTION at91_usart_read,0203H
PUBLIC at91_usart_receive_frame
FUNCTION at91_usart_receive_frame,0203H
LOCFRAME CSTACK, 8, STACK
PUBLIC at91_usart_send_frame
FUNCTION at91_usart_send_frame,0203H
LOCFRAME CSTACK, 4, STACK
PUBLIC at91_usart_trig_cmd
FUNCTION at91_usart_trig_cmd,0203H
PUBLIC at91_usart_write
FUNCTION at91_usart_write,0203H
; C:\At91\software\projects\bench\Source\lib_at91.c
; 1 //*----------------------------------------------------------------------------
; 2 //* ATMEL Microcontroller Software Support - ROUSSET -
; 3 //*----------------------------------------------------------------------------
; 4 //* The software is delivered "AS IS" without warranty or condition of any
; 5 //* kind, either express, implied or statutory. This includes without
; 6 //* limitation any warranty or condition with respect to merchantability or
; 7 //* fitness for any particular purpose, or against the infringements of
; 8 //* intellectual property rights of others.
; 9 //*----------------------------------------------------------------------------
; 10 //* File Name : lib_at91.c
; 11 //* Object : bench for the AT91EB01, use PIO in input and
; 12 //* output libraries definition
; 13 //*
; 14 //* 1.0 03/09/01 JPP : Creation
; 15 //*----------------------------------------------------------------------------
; 16
; 17
; 18 #include "periph/pio/lib_pio.h"
; 19 #include "periph/power_saving/lib_power_save.h"
; 20 #include "periph/power_saving/ps40800.h"
; 21 #include "parts/m40800/lib_m40800.h"
; 22 #include "periph/usart/lib_usart.h"
; 23 #include "periph/power_saving/lib_power_save.h"
; 24 #include "periph/timer_counter/tc.h"
; 25 #include "periph/timer_counter/lib_tc.h"
; 26 #include "periph/power_saving/lib_power_save.h"
; 27 #include "periph/stdc/lib_err.h"
; 28
; 29
; 30 /*-----------------*/
; 31 /* PIO Controllers */
; 32 /*-----------------*/
; 33
; 34 /* Instantiate PIO Controllers Pointers */
RSEG HUGE_I:HUGEDATA:SORT:NOROOT(2)
; 35 const StructPIO *Pio = PIO_BASE ;
Pio:
DS8 4
REQUIRE `?<Initializer for Pio>`
; 36
; 37 /* PIO Controller Descriptor */
RSEG HUGE_C:HUGECONST:SORT:NOROOT(2)
; 38 const PioCtrlDesc PIO_DESC =
PIO_DESC:
DC32 0FFFF0000H
DC8 8
DC8 31
DC8 0, 0
; 39 {
; 40 PIO_BASE,
; 41 PIO_ID,
; 42 NB_PIO
; 43 } ;
; 44
; 45
; 46 /*-------*/
; 47 /* USART */
; 48 /*-------*/
; 49
; 50 /* Usart 0 Descriptor */
RSEG HUGE_C:HUGECONST:SORT:NOROOT(2)
; 51 const UsartDesc USART0_DESC =
USART0_DESC:
DC32 0FFFD0000H
DC32 PIO_DESC
DC8 15
DC8 14
DC8 13
DC8 2
; 52 {
; 53 USART0_BASE,
; 54 &PIO_DESC,
; 55 PIORXD0,
; 56 PIOTXD0,
; 57 PIOSCK0,
; 58 US0_ID ,
; 59 } ;
; 60
; 61 /* Usart 1 Descriptor */
RSEG HUGE_C:HUGECONST:SORT:NOROOT(2)
; 62 const UsartDesc USART1_DESC =
USART1_DESC:
DC32 0FFFCC000H
DC32 PIO_DESC
DC8 22
DC8 21
DC8 20
DC8 3
; 63 {
; 64 USART1_BASE ,
; 65 &PIO_DESC,
; 66 PIORXD1,
; 67 PIOTXD1,
; 68 PIOSCK1,
; 69 US1_ID ,
; 70 } ;
; 71
; 72
; 73 /*------------------------*/
; 74 /* Timer Counter Channels */
; 75 /*------------------------*/
; 76
; 77 /* Timer Counter Channel 0 Descriptor */
RSEG HUGE_C:HUGECONST:SORT:NOROOT(2)
; 78 const TCDesc TC0_DESC =
TC0_DESC:
DC32 0FFFE0000H
DC32 PIO_DESC
DC8 4
DC8 1
DC8 2
DC8 0
; 79 {
; 80 TC0_BASE,
; 81 &PIO_DESC,
; 82 TC0_ID,
; 83 PIOTIOA0,
; 84 PIOTIOB0,
; 85 PIOTCLK0
; 86 } ;
; 87
; 88 /* Timer Counter Channel 1 Descriptor */
RSEG HUGE_C:HUGECONST:SORT:NOROOT(2)
; 89 const TCDesc TC1_DESC =
TC1_DESC:
DC32 0FFFE0040H
DC32 PIO_DESC
DC8 5
DC8 4
DC8 5
DC8 3
; 90 {
; 91 TC1_BASE,
; 92 &PIO_DESC,
; 93 TC1_ID,
; 94 PIOTIOA1,
; 95 PIOTIOB1,
; 96 PIOTCLK1
; 97 } ;
; 98
; 99 /* Timer Counter Channel 2 Descriptor */
RSEG HUGE_C:HUGECONST:SORT:NOROOT(2)
; 100 const TCDesc TC2_DESC =
TC2_DESC:
DC32 0FFFE0080H
DC32 PIO_DESC
DC8 6
DC8 7
DC8 8
DC8 6
; 101 {
; 102 TC2_BASE,
; 103 &PIO_DESC,
; 104 TC2_ID,
; 105 PIOTIOA2,
; 106 PIOTIOB2,
; 107 PIOTCLK2
; 108 } ;
; 109
; 110 /* Timer Counter Block Descriptor */
RSEG HUGE_C:HUGECONST:SORT:NOROOT(2)
; 111 const TCBlockDesc TCB_DESC =
TCB_DESC:
DC32 TC0_DESC
DC32 TC1_DESC
DC32 TC2_DESC
; 112 {
; 113 &TC0_DESC,
; 114 &TC1_DESC,
; 115 &TC2_DESC,
; 116 } ;
; 117
; 118
; 119
; 120 //*----------------------------------------------------------------------------
; 121 //* Function Name : at91_pio_open
; 122 //* Object : Setup pins to be Parallel IOs, as managed by the PIO
; 123 //* Input Parameters : <pio_pt> = PIO Controller Descriptor
; 124 //* : <mask> = bit mask identifying the PIOs
; 125 //* : <config> = mask identifying the PIOs configuration
; 126 //* Output Parameters : none
; 127 //* Functions called : none
; 128 //*----------------------------------------------------------------------------
RSEG NEARFUNC_A:CODE:NOROOT(2)
CFI Names cfiNames0
CFI StackFrame CFA SP HUGEDATA
CFI Resource R0:32, R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32
CFI Resource R8:32, R9:32, R10:32, R11:32, R12:32, SP:32, LR:32
CFI VirtualResource RET:32
CFI EndNames cfiNames0
CFI Common cfiCommon0 Using cfiNames0
CFI CodeAlign 4
CFI DataAlign 4
CFI ReturnAddress RET CODE
CFI CFA SP+0
CFI R0 Undefined
CFI R1 Undefined
CFI R2 Undefined
CFI R3 Undefined
CFI R4 SameValue
CFI R5 SameValue
CFI R6 SameValue
CFI R7 SameValue
CFI R8 SameValue
CFI R9 SameValue
CFI R10 SameValue
CFI R11 SameValue
CFI R12 Undefined
CFI LR Undefined
CFI RET LR
CFI EndCommon cfiCommon0
CFI Block cfiBlock0 Using cfiCommon0
CFI Function at91_pio_open
CODE32
; 129 void at91_pio_open ( const PioCtrlDesc *pio_pt, u_int mask, u_int config )
; 130 //* Begin
; 131 {
; 132 u_int x ;
; 133 //* If PIOs required to be output
; 134 if ((config & PIO_SENSE_BIT) != 0 )
at91_pio_open:
AND R3,R2,#+0xFF ;; Zero extend
TST R3,#+0x1
LDR R3,[R0, #+0]
; 135 {
; 136 //* Defines the PIOs as output
; 137 pio_pt->pio_base->PIO_OER = mask ;
STRNE R1,[R3, #+16]
; 138 }
; 139 //* Else
; 140 else
; 141 {
; 142 //* Defines the PIOs as inputmessage
; 143 pio_pt->pio_base->PIO_ODR = mask ;
STREQ R1,[R3, #+20]
; 144 }
; 145
; 146 //* If PIOs required to be filtered
; 147 if ((config & PIO_FILTER_BIT) != 0 )
AND R3,R2,#+0xFF ;; Zero extend
TST R3,#+0x2
LDR R3,[R0, #+0]
; 148 {
; 149 //* Enable the filter on PIOs
; 150 pio_pt->pio_base->PIO_IFER = mask ;
STRNE R1,[R3, #+32]
; 151 }
; 152 else
; 153 {
; 154 //* Disable the filter on PIOs
; 155 pio_pt->pio_base->PIO_IFDR = mask ;
STREQ R1,[R3, #+36]
; 156 }
; 157
; 158 //* If PIOs required to be open-drain
; 159 if ((config & PIO_OPENDRAIN_BIT) != 0 )
AND R3,R2,#+0xFF ;; Zero extend
TST R3,#+0x4
LDR R3,[R0, #+0]
; 160 {
; 161 //* Enable the filter on PIOs
; 162 pio_pt->pio_base->PIO_MDER = mask ;
STRNE R1,[R3, #+80]
; 163 }
; 164 else
; 165 {
; 166 //* Disable the filter on PIOs
; 167 pio_pt->pio_base->PIO_MDSR = mask ;
STREQ R1,[R3, #+88]
; 168 }
; 169
; 170 //* If PIOs required for an input change interrupt
; 171 if ((config & PIO_INPUT_IRQ_BIT) != 0 )
AND R2,R2,#+0xFF ;; Zero extend
TST R2,#+0x8
LDR R2,[R0, #+0]
; 172 {
; 173 //* Remove any interrupt */
; 174 x = pio_pt->pio_base->PIO_ISR ;
LDRNE R3,[R2, #+76]
; 175 //* Enable the Input Change Interrupt on PIOs
; 176 pio_pt->pio_base->PIO_IER = mask ;
STRNE R1,[R2, #+64]
; 177 }
; 178 else
; 179 {
; 180 //* Disable the Input Change Interrupt on PIOs
; 181 pio_pt->pio_base->PIO_IDR = mask ;
STREQ R1,[R2, #+68]
; 182 }
; 183
; 184 //* Defines the pins to be controlled by PIO Controller
; 185 pio_pt->pio_base->PIO_PER = mask ;
B ??Subroutine0_0
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