📄 cstartup_ice.arm
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;------------------------------------------------------------------------------
;- ATMEL Microcontroller Software Support - ROUSSET -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File source : cstartup_ice.s
;- Object : Boot for simulate Final Application version to be
;- loaded in SRAM. Only change as the internal RAM address
;- and support the Semihosting
;-
;- 1.0 06/04/00 JPP : Creation
;- 1.1 18/08/00 JCZ : Over-comment and optimize
;- 1.2 25/10/00 JPP : Global for including
;------------------------------------------------------------------------------
;--------------------------
;- Internal RAM Definition
;--------------------------
RAM_SIZE EQU (8*1024)
RAM_BASE EQU (0x00000000)
RAM_LIMIT EQU (RAM_BASE + RAM_SIZE)
;- The internal RAM is mapped at address 0x00300000 after reset until
;- Remap command is performed on the EBI.
RAM_BASE_BOOT EQU 0x00300000
;--------------------------------------------------------------
;- Power Saving Controller User Interface Structure Definition
;--------------------------------------------------------------
^ 0
PS_CR # 4 ;- Control Register
PS_PCER # 4 ;- Peripheral Clock Enable Register
PS_PCDR # 4 ;- Peripheral Clock Disable Register
PS_PCSR # 4 ;- Peripheral Clock Status Register
;------------------------------------------
;- AIC User Interface Structure Definition
;------------------------------------------
^ 0
AIC_SMR # 32*4 ;- Source Mode Register
AIC_SVR # 32*4 ;- Source Vector Register
AIC_IVR # 4 ;- IRQ Vector Register
AIC_FVR # 4 ;- FIQ Vector Register
AIC_ISR # 4 ;- Interrupt Status Register
AIC_IPR # 4 ;- Interrupt Pending Register
AIC_IMR # 4 ;- Interrupt Mask Register
AIC_CISR # 4 ;- Core Interrupt Status Register
# 4 ;- Reserved 0
# 4 ;- Reserved 1
AIC_IECR # 4 ;- Interrupt Enable Command Register
AIC_IDCR # 4 ;- Interrupt Disable Command Register
AIC_ICCR # 4 ;- Interrupt Clear Command Register
AIC_ISCR # 4 ;- Interrupt Set Command Register
AIC_EOICR # 4 ;- of Interrupt Command Register
AIC_SPU # 4 ;- Spurious Vector Register
;---------------------------------------------
;- AIC_SMR[]: Interrupt Source Mode Registers
;---------------------------------------------
AIC_PRIOR EQU 0x07 ;- Priority
AIC_SRCTYPE EQU 0x60 ;- Source Type Definition
AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU 0x00 ;- Level Sensitive
AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU 0x20 ;- Edge Triggered
AIC_SRCTYPE_EXT_LOW_LEVEL EQU 0x00 ;- Low Level
AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU 0x20 ;- Negative Edge
AIC_SRCTYPE_EXT_HIGH_LEVEL EQU 0x40 ;- High Level
AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU 0x60 ;- Positive Edge
;--------------------------------------
;- AIC_ISR: Interrupt Status Register
;--------------------------------------
AIC_IRQID EQU 0x1F ;- Current source interrupt
;-------------------------------------------
;- AIC_CISR: Interrupt Core Status Register
;-------------------------------------------
AIC_NFIQ EQU 0x01 ;- Core FIQ Status
AIC_NIRQ EQU 0x02 ;- Core IRQ Status
;--------------------------------------------
;- Advanced Interrupt COntroller BAse Address
;--------------------------------------------
AIC_BASE EQU 0xFFFFF000
EBI_BASE EQU 0xFFE00000 ;
PS_BASE EQU 0xFFFF4000
;--------------------------------------------
;- AT91EB40 External Memories Definition
;---------------------------------------
;- Flash Memory : AT29LV1024 64k*16
FLASH_BASE EQU 0x01000000
EXT_SRAM_BASE EQU 0x02000000
EXT_SRAM_SIZE EQU (512*1024) ; 512 Kbytes
EXT_SRAM_LIMIT EQU (EXT_SRAM_BASE+EXT_SRAM_SIZE)
;------------------------------------------------------------------------------
;- EBI Initialization Data
;-------------------------
;- The EBI User Interface Image which is copied by the boot.
;- 32,768MHz master clock assumed.
;- That's hardware! Details in the Electrical Datasheet of the AT91 device.
;- EBI Base Address is added at the end for commodity in copy code.
;------------------------------------------------------------------------------
EBI_CSR_0 EQU (FLASH_BASE :OR: 0x2529) ; 0x01000000, 16MB, 2 tdf, 16 bits, 2 WS
EBI_CSR_1 EQU (EXT_SRAM_BASE :OR: 0x2121) ; 0x02000000, 16MB, 0 hold, 16 bits, 1 WS
EBI_CSR_2 EQU 0x20000000 ; unused
EBI_CSR_3 EQU 0x30000000 ; unused
EBI_CSR_4 EQU 0x40000000 ; unused
EBI_CSR_5 EQU 0x50000000 ; unused
EBI_CSR_6 EQU 0x60000000 ; unused
EBI_CSR_7 EQU 0x70000000 ; unused
;--------------------------------
;- ARM Core Mode and Status Bits
;--------------------------------
ARM_MODE_USER EQU 0x10
ARM_MODE_FIQ EQU 0x11
ARM_MODE_IRQ EQU 0x12
ARM_MODE_SVC EQU 0x13
ARM_MODE_ABORT EQU 0x17
ARM_MODE_UNDEF EQU 0x1B
ARM_MODE_SYS EQU 0x1F
I_BIT EQU 0x80
F_BIT EQU 0x40
T_BIT EQU 0x20
;------------------------------------------------------------------------------
;- Area Definition
;-----------------
;- Must be defined as function to put first in the code as it must be mapped
;- at SRAM.
;------------------------------------------------------------------------------
AREA reset, CODE, READONLY, INTERWORK
;------------------------------------------------------------------------------
;- Semihosting support
;--------------------------------
;- The C runtime library is the IO functions provided by the semihosting.
;- They are generally costly in code and can be used as the debugger mode (ICE)
;------------------------------------------------------------------------------
;- Define "__main" to ensure that C runtime system is not linked
EXPORT __main
__main::
;------------------------------------------------------------------------------
;- Define the entry point
;------------------------
;- Note on the link address and the Remap command.
;- In order to guarantee that the non position-independant code (the ARM linker
;- armlink doesn't generate position-independant code) can work on the ARM,
;- it must be linked at address at which it expects to run.
;- In this startup example, we use RAM as base address.
;------------------------------------------------------------------------------
ENTRY
;------------------------------------------------------------------------------
;- Exception vectors
;--------------------
;- In the ICE function your board as run the boot code and initialize the remap
;- feature. but these code it's location independant and can be emulate the csartup_fash
;- fonctionnality.
;- These vectors are read at RAM address. in Flash mode these vectors are at 0
;- They absolutely requires to be in relative addresssing mode in order to
;- guarantee a valid jump. For the moment, all are just looping (what may be
;- dangerous in a final system). If an exception occurs before remap, this
;- would result in an infinite loop.
;------------------------------------------------------------------------------
B InitReset ; reset
undefvec
B undefvec ; Undefined Instruction
swivec
B swivec ; Software Interrupt
pabtvec
B pabtvec ; Prefetch Abort
dabtvec
B dabtvec ; Data Abort
rsvdvec
B rsvdvec ; reserved
irqvec
B irqvec ; reserved
fiqvec
B fiqvec ; reserved
;------------------------------------------------------------------------------
;- Exception vectors ( after cstartup execution )
;------------------------------------
;- These vectors are read at RAM address after the remap command is performed in
;- the EBI. As they will be relocated at address 0x0 to be effective, a
;- relative addressing is forbidden. The only possibility to get an absolute
;- addressing for an ARM vector is to read a PC relative value at a defined
;- offset. It is easy to reserve the locations 0x20 to 0x3C (the 8 next
;- vectors) for storing the absolute exception handler address.
;- The AIC vectoring access vectors are saved in the interrupt and fast
;- interrupt ARM vectors. So, only 5 offsets are required ( reserved vector
;- offset is never used).
;- The provisory handler addresses are defined on infinite loop and can be
;- modified at any time.
;- Note also that the reset is only accessible by a jump from the application
;- to 0. It is an actual software reset.
;- As the 13 first location are used by the vectors, the read/write link
;- address must be defined from 0x34 if internal data mapping is required.
;- (use for that the option -rw- base=0x34
;------------------------------------------------------------------------------
VectorTable
ldr pc, [pc, #&18] ; SoftReset
ldr pc, [pc, #&18] ; UndefHandler
ldr pc, [pc, #&18] ; SWIHandler
ldr pc, [pc, #&18] ; PrefetchAbortHandler
ldr pc, [pc, #&18] ; DataAbortHandler
nop ; Reserved
ldr pc, [pc,#-0xF20] ; IRQ : read the AIC
ldr pc, [pc,#-0xF20] ; FIQ : read the AIC
;- There are only 5 offsets as the vectoring is used.
DCD SoftReset
DCD UndefHandler
DCD SWIHandler
DCD PrefetchAbortHandler
DCD DataAbortHandler
;- Vectoring Execution function run at absolut addresss
SoftReset
b SoftReset
UndefHandler
b UndefHandler
SWIHandler
b SWIHandler
PrefetchAbortHandler
b PrefetchAbortHandler
DataAbortHandler
b DataAbortHandler
;------------------------------------------------------------------------------
;- EBI Initialization Data
;-------------------------
;- The EBI values depend to target choice , Clock, and memories access time.
;- Yous must be define these values in include file
;- The EBI User Interface Image which is copied by the boot.
;- The EBI_CSR_x are defined in the target and hardware depend.
;- That's hardware! Details in the Electrical Datasheet of the AT91 device.
;- EBI Base Address is added at the end for commodity in copy code.
;- ICE note :For ICE debug no need to set the EBI value these values already set
;- by the boot function.
;------------------------------------------------------------------------------
InitTableEBI
DCD EBI_CSR_0
DCD EBI_CSR_1
DCD EBI_CSR_2
DCD EBI_CSR_3
DCD EBI_CSR_4
DCD EBI_CSR_5
DCD EBI_CSR_6
DCD EBI_CSR_7
DCD 0x00000001 ; REMAP command
DCD 0x00000006 ; 6 memory regions, standard read
PtEBIBase
DCD EBI_BASE ; EBI Base Address
;------------------------------------------------------------------------------
;- The reset handler before Remap
;--------------------------------
;- From here, the code is executed from SRAM address
;------------------------------------------------------------------------------
InitReset
;------------------------------------------------------------------------------
;- Speed up the Boot sequence
;----------------------------
;- After reset, the number os wait states on chip select 0 is 8. All AT91
;- Evaluation Boards fits fast flash memories, so that the number of wait
;- states can be optimized to fast up the boot sequence.
;- ICE note :For ICE debug no need to set the EBI value these values already set
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