cstartup_ice.paf.arm

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

#define RAM_SIZE                 (8*1024)
#define RAM_BASE                 (0x00000000)
#define RAM_LIMIT                (RAM_BASE + RAM_SIZE)





#define RAM_BASE_BOOT            0x00300000



































#define AIC_PRIOR                            0x07    

#define AIC_SRCTYPE                          0x60    
#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE      0x00    
#define AIC_SRCTYPE_INT_EDGE_TRIGGERED       0x20    
#define AIC_SRCTYPE_EXT_LOW_LEVEL            0x00    
#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE        0x20    
#define AIC_SRCTYPE_EXT_HIGH_LEVEL           0x40    
#define AIC_SRCTYPE_EXT_POSITIVE_EDGE        0x60    





#define AIC_IRQID                    0x1F            





#define AIC_NFIQ                     0x01            
#define AIC_NIRQ                     0x02            





#define AIC_BASE                  0xFFFFF000
#define EBI_BASE        	      0xFFE00000      
#define PS_BASE                   0xFFFF4000




#define FLASH_BASE           0x01000000

#define EXT_SRAM_BASE        0x02000000
#define EXT_SRAM_SIZE        (512*1024)                   
#define EXT_SRAM_LIMIT       (EXT_SRAM_BASE+EXT_SRAM_SIZE)









#define EBI_CSR_0   	     (FLASH_BASE  |  0x2529)    
#define EBI_CSR_1   	     (EXT_SRAM_BASE  |  0x2121) 
#define EBI_CSR_2   	     0x20000000  
#define EBI_CSR_3   	     0x30000000  
#define EBI_CSR_4   	     0x40000000  
#define EBI_CSR_5   	     0x50000000  
#define EBI_CSR_6   	     0x60000000  
#define EBI_CSR_7   	     0x70000000  





#define ARM_MODE_USER                0x10
#define ARM_MODE_FIQ                 0x11
#define ARM_MODE_IRQ                 0x12
#define ARM_MODE_SVC                 0x13
#define ARM_MODE_ABORT               0x17
#define ARM_MODE_UNDEF               0x1B
#define ARM_MODE_SYS                 0x1F

#define I_BIT                        0x80
#define F_BIT                        0x40
#define T_BIT                        0x20







;.section ".reset","ax" 
;.reset
#line 148








                EXPORT      __main
__main::










                __ENTRY::













                B           InitReset       
undefvec
                B           undefvec        
swivec
                B           swivec          
pabtvec
                B           pabtvec         
dabtvec
                B           dabtvec         
rsvdvec
                B           rsvdvec         
irqvec
                B           irqvec          
fiqvec
                B           fiqvec          





















VectorTable
                ldr         pc, [pc, &18]          
                ldr         pc, [pc, &18]          
                ldr         pc, [pc, &18]          
                ldr         pc, [pc, &18]          
                ldr         pc, [pc, &18]          
                nop                                 
                ldr         pc, [pc,-0xF20]        
                ldr         pc, [pc,-0xF20]        


                
DCD         SoftReset
                
DCD         UndefHandler
                
DCD         SWIHandler
                
DCD         PrefetchAbortHandler
                
DCD         DataAbortHandler

SoftReset
                b           SoftReset
UndefHandler
                b           UndefHandler
SWIHandler
                b           SWIHandler
PrefetchAbortHandler
                b           PrefetchAbortHandler
DataAbortHandler
                b           DataAbortHandler













InitTableEBI
            
DCD         EBI_CSR_0
            
DCD         EBI_CSR_1
            
DCD         EBI_CSR_2
            
DCD         EBI_CSR_3
            
DCD         EBI_CSR_4
            
DCD         EBI_CSR_5
            
DCD         EBI_CSR_6
            
DCD         EBI_CSR_7
            
DCD         0x00000001  
            
DCD         0x00000006  
PtEBIBase
            
DCD         EBI_BASE    






InitReset











                ldr     r0, PtEBIBase
                ldr     r1, [pc,-(8+.-InitTableEBI)] 


                str     r1, [r0]








                bl      __low_level_init








                 add     r0, pc,AicData-8-.  

                ldmia   r0, {r1-r4}


                str     r4, [r1, 0x134]      




                mov         r0, 8
LoopAic0
                str         r1, [r1, 0x130]    
                subs        r0, r0, 1
                bhi         LoopAic0


                str     r2, [r1, 0x80]      
                add     r1, r1, 0x80
                mov     r0, 31                 
LoopAic1
                str     r3, [r1, r0, LSL 2]    
                subs    r0, r0, 1              
                bhi     LoopAic1

                b       EndInitAic


AicData
                
DCD     AIC_BASE                







                IMPORT  at91_default_fiq_handler
                IMPORT  at91_default_irq_handler
                IMPORT  at91_spurious_handler
PtDefaultHandler
                
DCD     at91_default_fiq_handler
                
DCD     at91_default_irq_handler
                
DCD     at91_spurious_handler
EndInitAic
















                mov     r8,RAM_BASE            

                sub     r9, pc,8+.-VectorTable  
                ldmia   r9!, {r0-r7}            

                stmia   r8!, {r0-r7}            
                ldmia   r9!, {r0-r4}            
                stmia   r8!, {r0-r4}            
















                sub     r10, pc,(8+.-InitTableEBI) 
                ldr     r12, PtInitRemap        


                ldmia   r10!, {r0-r9,r11}       
                stmia   r11!, {r0-r9}           


                mov     pc, r12                 

PtInitRemap
                
DCD     InitRemap               






InitRemap














#define IRQ_STACK_SIZE           (3*8*4)     
#define FIQ_STACK_SIZE           (3*4)       
#define ABT_STACK_SIZE           (1*4)       
#define UND_STACK_SIZE           (1*4)       










#define TOP_EXCEPTION_STACK          RAM_LIMIT           
#define TOP_APPLICATION_STACK        EXT_SRAM_LIMIT      




                ldr     r0, =TOP_EXCEPTION_STACK


                msr     CPSR_c, ARM_MODE_FIQ | I_BIT | F_BIT
                mov     r13, r0                     
                sub     r0, r0, FIQ_STACK_SIZE


                msr     CPSR_c, ARM_MODE_IRQ | I_BIT | F_BIT
                mov     r13, r0                     
                sub     r0, r0, IRQ_STACK_SIZE


                msr     CPSR_c, ARM_MODE_ABORT | I_BIT | F_BIT
                mov     r13, r0                     
                sub     r0, r0, ABT_STACK_SIZE


                msr     CPSR_c, ARM_MODE_UNDEF | I_BIT | F_BIT
                mov     r13, r0                     
                sub     r0, r0, UND_STACK_SIZE


                msr     CPSR_c, ARM_MODE_SVC | I_BIT | F_BIT
                mov     r13, r0                     
                sub     r0, r0, UND_STACK_SIZE









 .weak __ghsend_stack
 .weak __ghsbegin_heap
                msr     CPSR_c, ARM_MODE_USER      
                ldr     R13, =__ghsend_stack

                ldr     r12, =__ghsbegin_heap   






 
 
 .weak __ghsbegin_bss
 .weak __ghsend_bss

                ldr         r1, =__ghsend_bss     
                ldr         r3, =__ghsbegin_bss   
 		mov         r2, 0
 LoopZI
 		cmp         r3, r1
                strcc       r2, [r3], 4
                bcc         LoopZI

 
 
 .weak __ghsbegin_sbss
 .weak __ghsend_sbss

                ldr         r1, =__ghsend_sbss    
                ldr         r3, =__ghsbegin_sbss  
 		mov         r2, 0
 LoopZI2
 		cmp         r3, r1
                strcc       r2, [r3], 4
                bcc         LoopZI2

 
 
 .weak __ghsbegin_data
 .weak __ghsend_data
 .weak __ghsbegin_romdata

                ldr         r0, =__ghsbegin_romdata 
                ldr         r1, =__ghsbegin_data    
                ldr         r3, =__ghsend_data      
 LoopRW
 		cmp         r1, r3
                ldrcc       r2, [r0], 4
 		strcc       r2, [r1], 4
                bcc         LoopRW








                IMPORT      main

                ldr         r0, =main
                mov         lr, pc
                bx          r0






End_loop
                b           End_loop






__low_level_init
                mvn         r0,0               
                ldr         r1,=PS_BASE         
                str         r0,[r1, 0x4]   
                mov         pc,r14

				END