📄 cstartup_flash.s
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;------------------------------------------------------------------------------
;- ATMEL Microcontroller Software Support - ROUSSET -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File source : cstartup_flash.s
;- Object : Boot for the Flash Uploader
;-
;- 03/07/00 EL : Creation
;- 07/07/00 EL : Supress CS1
;- 31/01/02 PFi : Test signal on pin PIO1, 2 and 4 has been removed.
;- : Port to ARM ADS v1.1
;------------------------------------------------------------------------------
AREA reset, CODE, READONLY, INTERWORK
INCLUDE targets/eb40/eb40.inc
;- Stack Sizes Definition
IRQ_STACK_SIZE EQU (4*4)
STACK_LIMIT EQU 0x1000
IMPORT main
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
;- Define "__main" to ensure that C runtime system is not linked
EXPORT __main
__main
;------------------------------------------------------------------------------
;- Define the entry point
ENTRY
;- Exception vectors
;- -----------------
rstvec
B InitReset ; reset
undefvec
B undefvec ; Undefined Instruction
swivec
B swivec ; Software Interrupt
pabtvec
B pabtvec ; Prefetch Abort
dabtvec
B dabtvec ; Data Abort
rsvdvec
B rsvdvec ; reserved
irqvec
ldr pc, [pc,#-0xF20] ; IRQ : read the AIC
fiqvec
ldr pc, [pc,#-0xF20] ; FIQ : read the AIC
;- EBI Initialization Data
;-------------------------
; 32,768MHz master clock assumed
InitTableEBI
DCD 0x01002529 ; 0x01000000, 16MB, 2 tdf, 16 bits, 2 WS
;- System Peripheral Base Addresses
;----------------------------------
PtEBIBase
DCD EBI_BASE ; EBI Base Address
DCD AIC_BASE ; AIC BAse Address
InitReset
;- Speed up the Boot sequence
;----------------------------
;- | Load System EBI Base address and CSR0 Init Value
ldr r0, PtEBIBase
ldr r1, InitTableEBI
;- | Speed up the EBI by disabling wait state on Chip Select 0
str r1, [r0]
;- Get the Area Base and Limit
mov r0, #0
ldr r1, =|Image$$RO$$Limit|
ldr r2, =0x300000
CopyLoop
ldr r10, [r0], #4
str r10, [r2], #4
cmp r0, r1
blo CopyLoop
;- Initialise the Memory Controller
;----------------------------------
;- | Copy the Image of the Memory Controller
adr r10, InitTableEBI ; get the address of the chip select register image
; do the remap
ldr r0, =EBI_BASE
mov r1, #1
str r1, [r0, #EBI_RCR]
mov r1, #6
str r1, [r0, #EBI_MCR]
InitRemap
;- Setup the stack for each mode
;-------------------------------
;- | Set up Interrupt mode and set IRQ stack
msr CPSR_c, #ARM_MODE_IRQ:OR:I_BIT:OR:F_BIT
ldr r13, =STACK_LIMIT
mov r0, r13
sub r0, r0, #IRQ_STACK_SIZE
;- | Set up the User mode and stack pointer
msr cpsr_c, #ARM_MODE_SYS:OR:I_BIT:OR:F_BIT ; No interrupts
mov r13, r0
;- Setup Application Operating Mode and Enable the interrupts
;- ----------------------------------------------------------
msr cpsr_c, #ARM_MODE_USER
mov r13, r0
;- | Branch on C code Main function (with interworking)
ldr r0, =main
mov lr, pc
bx r0
END
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