at91r40008.rdf

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

AT91C_PIO_ODR.byteEndian=little
AT91C_PIO_ODR.type=enum
AT91C_PIO_ODR.enum.0.name=*** Write only ***
AT91C_PIO_ODR.enum.1.name=Error
# ========== Register definition for TC2 peripheral ========== 
AT91C_TC2_IDR.name="AT91C_TC2_IDR"
AT91C_TC2_IDR.description="Interrupt Disable Register"
AT91C_TC2_IDR.helpkey="Interrupt Disable Register"
AT91C_TC2_IDR.access=memorymapped
AT91C_TC2_IDR.address=0xFFFE00A8
AT91C_TC2_IDR.width=32
AT91C_TC2_IDR.byteEndian=little
AT91C_TC2_IDR.type=enum
AT91C_TC2_IDR.enum.0.name=*** Write only ***
AT91C_TC2_IDR.enum.1.name=Error
AT91C_TC2_SR.name="AT91C_TC2_SR"
AT91C_TC2_SR.description="Status Register"
AT91C_TC2_SR.helpkey="Status Register"
AT91C_TC2_SR.access=memorymapped
AT91C_TC2_SR.address=0xFFFE00A0
AT91C_TC2_SR.width=32
AT91C_TC2_SR.byteEndian=little
AT91C_TC2_SR.permission.write=none
AT91C_TC2_RB.name="AT91C_TC2_RB"
AT91C_TC2_RB.description="Register B"
AT91C_TC2_RB.helpkey="Register B"
AT91C_TC2_RB.access=memorymapped
AT91C_TC2_RB.address=0xFFFE0098
AT91C_TC2_RB.width=32
AT91C_TC2_RB.byteEndian=little
AT91C_TC2_CV.name="AT91C_TC2_CV"
AT91C_TC2_CV.description="Counter Value"
AT91C_TC2_CV.helpkey="Counter Value"
AT91C_TC2_CV.access=memorymapped
AT91C_TC2_CV.address=0xFFFE0090
AT91C_TC2_CV.width=32
AT91C_TC2_CV.byteEndian=little
AT91C_TC2_CCR.name="AT91C_TC2_CCR"
AT91C_TC2_CCR.description="Channel Control Register"
AT91C_TC2_CCR.helpkey="Channel Control Register"
AT91C_TC2_CCR.access=memorymapped
AT91C_TC2_CCR.address=0xFFFE0080
AT91C_TC2_CCR.width=32
AT91C_TC2_CCR.byteEndian=little
AT91C_TC2_CCR.type=enum
AT91C_TC2_CCR.enum.0.name=*** Write only ***
AT91C_TC2_CCR.enum.1.name=Error
AT91C_TC2_IMR.name="AT91C_TC2_IMR"
AT91C_TC2_IMR.description="Interrupt Mask Register"
AT91C_TC2_IMR.helpkey="Interrupt Mask Register"
AT91C_TC2_IMR.access=memorymapped
AT91C_TC2_IMR.address=0xFFFE00AC
AT91C_TC2_IMR.width=32
AT91C_TC2_IMR.byteEndian=little
AT91C_TC2_IMR.permission.write=none
AT91C_TC2_IER.name="AT91C_TC2_IER"
AT91C_TC2_IER.description="Interrupt Enable Register"
AT91C_TC2_IER.helpkey="Interrupt Enable Register"
AT91C_TC2_IER.access=memorymapped
AT91C_TC2_IER.address=0xFFFE00A4
AT91C_TC2_IER.width=32
AT91C_TC2_IER.byteEndian=little
AT91C_TC2_IER.type=enum
AT91C_TC2_IER.enum.0.name=*** Write only ***
AT91C_TC2_IER.enum.1.name=Error
AT91C_TC2_RC.name="AT91C_TC2_RC"
AT91C_TC2_RC.description="Register C"
AT91C_TC2_RC.helpkey="Register C"
AT91C_TC2_RC.access=memorymapped
AT91C_TC2_RC.address=0xFFFE009C
AT91C_TC2_RC.width=32
AT91C_TC2_RC.byteEndian=little
AT91C_TC2_RA.name="AT91C_TC2_RA"
AT91C_TC2_RA.description="Register A"
AT91C_TC2_RA.helpkey="Register A"
AT91C_TC2_RA.access=memorymapped
AT91C_TC2_RA.address=0xFFFE0094
AT91C_TC2_RA.width=32
AT91C_TC2_RA.byteEndian=little
AT91C_TC2_CMR.name="AT91C_TC2_CMR"
AT91C_TC2_CMR.description="Channel Mode Register"
AT91C_TC2_CMR.helpkey="Channel Mode Register"
AT91C_TC2_CMR.access=memorymapped
AT91C_TC2_CMR.address=0xFFFE0084
AT91C_TC2_CMR.width=32
AT91C_TC2_CMR.byteEndian=little
# ========== Register definition for TC1 peripheral ========== 
AT91C_TC1_IDR.name="AT91C_TC1_IDR"
AT91C_TC1_IDR.description="Interrupt Disable Register"
AT91C_TC1_IDR.helpkey="Interrupt Disable Register"
AT91C_TC1_IDR.access=memorymapped
AT91C_TC1_IDR.address=0xFFFE0068
AT91C_TC1_IDR.width=32
AT91C_TC1_IDR.byteEndian=little
AT91C_TC1_IDR.type=enum
AT91C_TC1_IDR.enum.0.name=*** Write only ***
AT91C_TC1_IDR.enum.1.name=Error
AT91C_TC1_SR.name="AT91C_TC1_SR"
AT91C_TC1_SR.description="Status Register"
AT91C_TC1_SR.helpkey="Status Register"
AT91C_TC1_SR.access=memorymapped
AT91C_TC1_SR.address=0xFFFE0060
AT91C_TC1_SR.width=32
AT91C_TC1_SR.byteEndian=little
AT91C_TC1_SR.permission.write=none
AT91C_TC1_RB.name="AT91C_TC1_RB"
AT91C_TC1_RB.description="Register B"
AT91C_TC1_RB.helpkey="Register B"
AT91C_TC1_RB.access=memorymapped
AT91C_TC1_RB.address=0xFFFE0058
AT91C_TC1_RB.width=32
AT91C_TC1_RB.byteEndian=little
AT91C_TC1_CV.name="AT91C_TC1_CV"
AT91C_TC1_CV.description="Counter Value"
AT91C_TC1_CV.helpkey="Counter Value"
AT91C_TC1_CV.access=memorymapped
AT91C_TC1_CV.address=0xFFFE0050
AT91C_TC1_CV.width=32
AT91C_TC1_CV.byteEndian=little
AT91C_TC1_CCR.name="AT91C_TC1_CCR"
AT91C_TC1_CCR.description="Channel Control Register"
AT91C_TC1_CCR.helpkey="Channel Control Register"
AT91C_TC1_CCR.access=memorymapped
AT91C_TC1_CCR.address=0xFFFE0040
AT91C_TC1_CCR.width=32
AT91C_TC1_CCR.byteEndian=little
AT91C_TC1_CCR.type=enum
AT91C_TC1_CCR.enum.0.name=*** Write only ***
AT91C_TC1_CCR.enum.1.name=Error
AT91C_TC1_IMR.name="AT91C_TC1_IMR"
AT91C_TC1_IMR.description="Interrupt Mask Register"
AT91C_TC1_IMR.helpkey="Interrupt Mask Register"
AT91C_TC1_IMR.access=memorymapped
AT91C_TC1_IMR.address=0xFFFE006C
AT91C_TC1_IMR.width=32
AT91C_TC1_IMR.byteEndian=little
AT91C_TC1_IMR.permission.write=none
AT91C_TC1_IER.name="AT91C_TC1_IER"
AT91C_TC1_IER.description="Interrupt Enable Register"
AT91C_TC1_IER.helpkey="Interrupt Enable Register"
AT91C_TC1_IER.access=memorymapped
AT91C_TC1_IER.address=0xFFFE0064
AT91C_TC1_IER.width=32
AT91C_TC1_IER.byteEndian=little
AT91C_TC1_IER.type=enum
AT91C_TC1_IER.enum.0.name=*** Write only ***
AT91C_TC1_IER.enum.1.name=Error
AT91C_TC1_RC.name="AT91C_TC1_RC"
AT91C_TC1_RC.description="Register C"
AT91C_TC1_RC.helpkey="Register C"
AT91C_TC1_RC.access=memorymapped
AT91C_TC1_RC.address=0xFFFE005C
AT91C_TC1_RC.width=32
AT91C_TC1_RC.byteEndian=little
AT91C_TC1_RA.name="AT91C_TC1_RA"
AT91C_TC1_RA.description="Register A"
AT91C_TC1_RA.helpkey="Register A"
AT91C_TC1_RA.access=memorymapped
AT91C_TC1_RA.address=0xFFFE0054
AT91C_TC1_RA.width=32
AT91C_TC1_RA.byteEndian=little
AT91C_TC1_CMR.name="AT91C_TC1_CMR"
AT91C_TC1_CMR.description="Channel Mode Register"
AT91C_TC1_CMR.helpkey="Channel Mode Register"
AT91C_TC1_CMR.access=memorymapped
AT91C_TC1_CMR.address=0xFFFE0044
AT91C_TC1_CMR.width=32
AT91C_TC1_CMR.byteEndian=little
# ========== Register definition for TC0 peripheral ========== 
AT91C_TC0_IDR.name="AT91C_TC0_IDR"
AT91C_TC0_IDR.description="Interrupt Disable Register"
AT91C_TC0_IDR.helpkey="Interrupt Disable Register"
AT91C_TC0_IDR.access=memorymapped
AT91C_TC0_IDR.address=0xFFFE0028
AT91C_TC0_IDR.width=32
AT91C_TC0_IDR.byteEndian=little
AT91C_TC0_IDR.type=enum
AT91C_TC0_IDR.enum.0.name=*** Write only ***
AT91C_TC0_IDR.enum.1.name=Error
AT91C_TC0_SR.name="AT91C_TC0_SR"
AT91C_TC0_SR.description="Status Register"
AT91C_TC0_SR.helpkey="Status Register"
AT91C_TC0_SR.access=memorymapped
AT91C_TC0_SR.address=0xFFFE0020
AT91C_TC0_SR.width=32
AT91C_TC0_SR.byteEndian=little
AT91C_TC0_SR.permission.write=none
AT91C_TC0_RB.name="AT91C_TC0_RB"
AT91C_TC0_RB.description="Register B"
AT91C_TC0_RB.helpkey="Register B"
AT91C_TC0_RB.access=memorymapped
AT91C_TC0_RB.address=0xFFFE0018
AT91C_TC0_RB.width=32
AT91C_TC0_RB.byteEndian=little
AT91C_TC0_CV.name="AT91C_TC0_CV"
AT91C_TC0_CV.description="Counter Value"
AT91C_TC0_CV.helpkey="Counter Value"
AT91C_TC0_CV.access=memorymapped
AT91C_TC0_CV.address=0xFFFE0010
AT91C_TC0_CV.width=32
AT91C_TC0_CV.byteEndian=little
AT91C_TC0_CCR.name="AT91C_TC0_CCR"
AT91C_TC0_CCR.description="Channel Control Register"
AT91C_TC0_CCR.helpkey="Channel Control Register"
AT91C_TC0_CCR.access=memorymapped
AT91C_TC0_CCR.address=0xFFFE0000
AT91C_TC0_CCR.width=32
AT91C_TC0_CCR.byteEndian=little
AT91C_TC0_CCR.type=enum
AT91C_TC0_CCR.enum.0.name=*** Write only ***
AT91C_TC0_CCR.enum.1.name=Error
AT91C_TC0_IMR.name="AT91C_TC0_IMR"
AT91C_TC0_IMR.description="Interrupt Mask Register"
AT91C_TC0_IMR.helpkey="Interrupt Mask Register"
AT91C_TC0_IMR.access=memorymapped
AT91C_TC0_IMR.address=0xFFFE002C
AT91C_TC0_IMR.width=32
AT91C_TC0_IMR.byteEndian=little
AT91C_TC0_IMR.permission.write=none
AT91C_TC0_IER.name="AT91C_TC0_IER"
AT91C_TC0_IER.description="Interrupt Enable Register"
AT91C_TC0_IER.helpkey="Interrupt Enable Register"
AT91C_TC0_IER.access=memorymapped
AT91C_TC0_IER.address=0xFFFE0024
AT91C_TC0_IER.width=32
AT91C_TC0_IER.byteEndian=little
AT91C_TC0_IER.type=enum
AT91C_TC0_IER.enum.0.name=*** Write only ***
AT91C_TC0_IER.enum.1.name=Error
AT91C_TC0_RC.name="AT91C_TC0_RC"
AT91C_TC0_RC.description="Register C"
AT91C_TC0_RC.helpkey="Register C"
AT91C_TC0_RC.access=memorymapped
AT91C_TC0_RC.address=0xFFFE001C
AT91C_TC0_RC.width=32
AT91C_TC0_RC.byteEndian=little
AT91C_TC0_RA.name="AT91C_TC0_RA"
AT91C_TC0_RA.description="Register A"
AT91C_TC0_RA.helpkey="Register A"
AT91C_TC0_RA.access=memorymapped
AT91C_TC0_RA.address=0xFFFE0014
AT91C_TC0_RA.width=32
AT91C_TC0_RA.byteEndian=little
AT91C_TC0_CMR.name="AT91C_TC0_CMR"
AT91C_TC0_CMR.description="Channel Mode Register"
AT91C_TC0_CMR.helpkey="Channel Mode Register"
AT91C_TC0_CMR.access=memorymapped
AT91C_TC0_CMR.address=0xFFFE0004
AT91C_TC0_CMR.width=32
AT91C_TC0_CMR.byteEndian=little
# ========== Register definition for TCB0 peripheral ========== 
AT91C_TCB0_BCR.name="AT91C_TCB0_BCR"
AT91C_TCB0_BCR.description="TC Block Control Register"
AT91C_TCB0_BCR.helpkey="TC Block Control Register"
AT91C_TCB0_BCR.access=memorymapped
AT91C_TCB0_BCR.address=0xFFFE00C0
AT91C_TCB0_BCR.width=32
AT91C_TCB0_BCR.byteEndian=little
AT91C_TCB0_BCR.type=enum
AT91C_TCB0_BCR.enum.0.name=*** Write only ***
AT91C_TCB0_BCR.enum.1.name=Error
AT91C_TCB0_BMR.name="AT91C_TCB0_BMR"
AT91C_TCB0_BMR.description="TC Block Mode Register"
AT91C_TCB0_BMR.helpkey="TC Block Mode Register"
AT91C_TCB0_BMR.access=memorymapped
AT91C_TCB0_BMR.address=0xFFFE00C4
AT91C_TCB0_BMR.width=32
AT91C_TCB0_BMR.byteEndian=little
AT91C_TCB0_BMR.permission.write=none
# ========== Register definition for PDC_US1 peripheral ========== 
AT91C_US1_TCR.name="AT91C_US1_TCR"
AT91C_US1_TCR.description="Transmit Counter Register"
AT91C_US1_TCR.helpkey="Transmit Counter Register"
AT91C_US1_TCR.access=memorymapped
AT91C_US1_TCR.address=0xFFFCC03C
AT91C_US1_TCR.width=32
AT91C_US1_TCR.byteEndian=little
AT91C_US1_RCR.name="AT91C_US1_RCR"
AT91C_US1_RCR.description="Receive Counter Register"
AT91C_US1_RCR.helpkey="Receive Counter Register"
AT91C_US1_RCR.access=memorymapped
AT91C_US1_RCR.address=0xFFFCC034
AT91C_US1_RCR.width=32
AT91C_US1_RCR.byteEndian=little
AT91C_US1_TPR.name="AT91C_US1_TPR"
AT91C_US1_TPR.description="Transmit Pointer Register"
AT91C_US1_TPR.helpkey="Transmit Pointer Register"
AT91C_US1_TPR.access=memorymapped
AT91C_US1_TPR.address=0xFFFCC038
AT91C_US1_TPR.width=32
AT91C_US1_TPR.byteEndian=little
AT91C_US1_RPR.name="AT91C_US1_RPR"
AT91C_US1_RPR.description="Receive Pointer Register"
AT91C_US1_RPR.helpkey="Receive Pointer Register"
AT91C_US1_RPR.access=memorymapped
AT91C_US1_RPR.address=0xFFFCC030
AT91C_US1_RPR.width=32
AT91C_US1_RPR.byteEndian=little
# ========== Register definition for US1 peripheral ========== 
AT91C_US1_RTOR.name="AT91C_US1_RTOR"
AT91C_US1_RTOR.description="Receiver Time-out Register"
AT91C_US1_RTOR.helpkey="Receiver Time-out Register"
AT91C_US1_RTOR.access=memorymapped
AT91C_US1_RTOR.address=0xFFFCC024
AT91C_US1_RTOR.width=32
AT91C_US1_RTOR.byteEndian=little
AT91C_US1_THR.name="AT91C_US1_THR"
AT91C_US1_THR.description="Transmitter Holding Register"
AT91C_US1_THR.helpkey="Transmitter Holding Register"
AT91C_US1_THR.access=memorymapped
AT91C_US1_THR.address=0xFFFCC01C
AT91C_US1_THR.width=32
AT91C_US1_THR.byteEndian=little
AT91C_US1_THR.type=enum
AT91C_US1_THR.enum.0.name=*** Write only ***
AT91C_US1_THR.enum.1.name=Error
AT91C_US1_CSR.name="AT91C_US1_CSR"
AT91C_US1_CSR.description="Channel Status Register"
AT91C_US1_CSR.helpkey="Channel Status Register"
AT91C_US1_CSR.access=memorymapped
AT91C_US1_CSR.address=0xFFFCC014
AT91C_US1_CSR.width=32
AT91C_US1_CSR.byteEndian=little
AT91C_US1_CSR.permission.write=none
AT91C_US1_IDR.name="AT91C_US1_IDR"
AT91C_US1_IDR.description="Interrupt Disable Register"
AT91C_US1_IDR.helpkey="Interrupt Disable Register"
AT91C_US1_IDR.access=memorymapped
AT91C_US1_IDR.address=0xFFFCC00C
AT91C_US1_IDR.width=32
AT91C_US1_IDR.byteEndian=little
AT91C_US1_IDR.type=enum
AT91C_US1_IDR.enum.0.name=*** Write only ***
AT91C_US1_IDR.enum.1.name=Error
AT91C_US1_MR.name="AT91C_US1_MR"
AT91C_US1_MR.description="Mode Register"
AT91C_US1_MR.helpkey="Mode Register"
AT91C_US1_MR.access=memorymapped
AT91C_US1_MR.address=0xFFFCC004
AT91C_US1_MR.width=32
AT91C_US1_MR.byteEndian=little
AT91C_US1_TTGR.name="AT91C_US1_TTGR"
AT91C_US1_TTGR.description="Transmitter Time-guard Register"
AT91C_US1_TTGR.helpkey="Transmitter Time-guard Register"
AT91C_US1_TTGR.access=memorymapped
AT91C_US1_TTGR.address=0xFFFCC028
AT91C_US1_TTGR.width=32
AT91C_US1_TTGR.byteEndian=little
AT91C_US1_BRGR.name="AT91C_US1_BRGR"
AT91C_US1_BRGR.description="Baud Rate Generator Register"
AT91C_US1_BRGR.helpkey="Baud Rate Generator Register"
AT91C_US1_BRGR.access=memorymapped
AT91C_US1_BRGR.address=0xFFFCC020
AT91C_US1_BRGR.width=32
AT91C_US1_BRGR.byteEndian=little
AT91C_US1_RHR.name="AT91C_US1_RHR"
AT91C_US1_RHR.description="Receiver Holding Register"
AT91C_US1_RHR.helpkey="Receiver Holding Register"
AT91C_US1_RHR.access=memorymapped
AT91C_US1_RHR.address=0xFFFCC018
AT91C_US1_RHR.width=32
AT91C_US1_RHR.byteEndian=little
AT91C_US1_RHR.permission.write=none
AT91C_US1_IMR.name="AT91C_US1_IMR"
AT91C_US1_IMR.description="Interrupt Mask Register"
AT91C_US1_IMR.helpkey="Interrupt Mask Register"
AT91C_US1_IMR.access=memorymapped
AT91C_US1_IMR.address=0xFFFCC010
AT91C_US1_IMR.width=32
AT91C_US1_IMR.byteEndian=little
AT91C_US1_IMR.permission.write=none
AT91C_US1_IER.name="AT91C_US1_IER"
AT91C_US1_IER.description="Interrupt Enable Register"
AT91C_US1_IER.helpkey="Interrupt Enable Register"