📄 lib_at91r40008.h
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//*----------------------------------------------------------------------------
//* \fn AT91F_US_SendFrame
//* \brief Return 1 if PDC has been initialized with Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_US_SendFrame(
AT91PS_USART pUSART,
char *pBuffer,
unsigned int szBuffer )
{
return AT91F_PDC_SendFrame(
(AT91PS_PDC) &(pUSART->US_RPR),
pBuffer,
szBuffer);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US_ReceiveFrame
//* \brief Return 1 if PDC has been initialized with Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_US_ReceiveFrame (
AT91PS_USART pUSART,
char *pBuffer,
unsigned int szBuffer )
{
return AT91F_PDC_ReceiveFrame(
(AT91PS_PDC) &(pUSART->US_RPR),
pBuffer,
szBuffer);
}
/* *****************************************************************************
SOFTWARE API FOR AIC
***************************************************************************** */
#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_ConfigureIt
//* \brief Interrupt Handler Initialization
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_AIC_ConfigureIt (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id, // \arg interrupt number to initialize
unsigned int priority, // \arg priority to give to the interrupt
unsigned int src_type, // \arg activation and sense of activation
void (*newHandler) (void) ) // \arg address of the interrupt handler
{
unsigned int oldHandler;
unsigned int mask ;
oldHandler = pAic->AIC_SVR[irq_id];
mask = 0x1 << irq_id ;
//* Disable the interrupt on the interrupt controller
pAic->AIC_IDCR = mask ;
//* Save the interrupt handler routine pointer and the interrupt priority
pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
//* Store the Source Mode Register
pAic->AIC_SMR[irq_id] = src_type | priority ;
//* Clear the interrupt on the interrupt controller
pAic->AIC_ICCR = mask ;
return oldHandler;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_EnableIt
//* \brief Enable corresponding IT number
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_EnableIt (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id ) // \arg interrupt number to initialize
{
//* Enable the interrupt on the interrupt controller
pAic->AIC_IECR = 0x1 << irq_id ;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_DisableIt
//* \brief Disable corresponding IT number
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_DisableIt (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id ) // \arg interrupt number to initialize
{
unsigned int mask = 0x1 << irq_id;
//* Disable the interrupt on the interrupt controller
pAic->AIC_IDCR = mask ;
//* Clear the interrupt on the Interrupt Controller ( if one is pending )
pAic->AIC_ICCR = mask ;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_ClearIt
//* \brief Clear corresponding IT number
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_ClearIt (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id) // \arg interrupt number to initialize
{
//* Clear the interrupt on the Interrupt Controller ( if one is pending )
pAic->AIC_ICCR = (0x1 << irq_id);
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_AcknowledgeIt
//* \brief Acknowledge corresponding IT number
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_AcknowledgeIt (
AT91PS_AIC pAic) // \arg pointer to the AIC registers
{
pAic->AIC_EOICR = pAic->AIC_EOICR;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_Trig
//* \brief Trig an IT
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_Trig (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id) // \arg interrupt number
{
pAic->AIC_ISCR = (0x1 << irq_id) ;
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_IsActive
//* \brief Test if an IT is active
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_AIC_IsActive (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id) // \arg Interrupt Number
{
return (pAic->AIC_ISR & (0x1 << irq_id));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_IsPending
//* \brief Test if an IT is pending
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_AIC_IsPending (
AT91PS_AIC pAic, // \arg pointer to the AIC registers
unsigned int irq_id) // \arg Interrupt Number
{
return (pAic->AIC_IPR & (0x1 << irq_id));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_EBI_CfgPIO
//* \brief Configure PIO controllers to drive EBI signals
//*----------------------------------------------------------------------------
__inline void AT91F_EBI_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIO, // PIO controller base address
((unsigned int) AT91C_P26_NCS2 ) |
((unsigned int) AT91C_P27_NCS3 ) |
((unsigned int) AT91C_P24_BMS ) |
((unsigned int) AT91C_P28_A20 ) |
((unsigned int) AT91C_P29_A21 ) |
((unsigned int) AT91C_P30_A22 ) |
((unsigned int) AT91C_P31_A23 ), // Peripheral A
((unsigned int) AT91C_P31_NCS4 ) |
((unsigned int) AT91C_P30_NCS5 ) |
((unsigned int) AT91C_P29_NCS6 ) |
((unsigned int) AT91C_P28_NCS7 )); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_WD_CfgPS
//* \brief Enable Peripheral clock in PMC for WD
//*----------------------------------------------------------------------------
__inline void AT91F_WD_CfgPS (void)
{
AT91F_PS_EnablePeriphClock(
AT91C_BASE_PS, // PIO controller base address
((unsigned int) 1 << AT91C_ID_WD));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgPS
//* \brief Enable Peripheral clock in PMC for PIO
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgPS (void)
{
AT91F_PS_EnablePeriphClock(
AT91C_BASE_PS, // PIO controller base address
((unsigned int) 1 << AT91C_ID_PIO));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIO_CfgPIO
//* \brief Configure PIO controllers to drive PIO signals
//*----------------------------------------------------------------------------
__inline void AT91F_PIO_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIO, // PIO controller base address
((unsigned int) AT91C_P25_MCKO ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US1_CfgPS
//* \brief Enable Peripheral clock in PMC for US1
//*----------------------------------------------------------------------------
__inline void AT91F_US1_CfgPS (void)
{
AT91F_PS_EnablePeriphClock(
AT91C_BASE_PS, // PIO controller base address
((unsigned int) 1 << AT91C_ID_US1));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US1_CfgPIO
//* \brief Configure PIO controllers to drive US1 signals
//*----------------------------------------------------------------------------
__inline void AT91F_US1_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIO, // PIO controller base address
((unsigned int) AT91C_P22_RXD1 ) |
((unsigned int) AT91C_P21_TXD1 ) |
((unsigned int) AT91C_P20_SCK1 ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US0_CfgPS
//* \brief Enable Peripheral clock in PMC for US0
//*----------------------------------------------------------------------------
__inline void AT91F_US0_CfgPS (void)
{
AT91F_PS_EnablePeriphClock(
AT91C_BASE_PS, // PIO controller base address
((unsigned int) 1 << AT91C_ID_US0));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US0_CfgPIO
//* \brief Configure PIO controllers to drive US0 signals
//*----------------------------------------------------------------------------
__inline void AT91F_US0_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIO, // PIO controller base address
((unsigned int) AT91C_P15_RXD0 ) |
((unsigned int) AT91C_P14_TXD0 ) |
((unsigned int) AT91C_P13_SCK0 ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_CfgPS
//* \brief Enable Peripheral clock in PMC for AIC
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_CfgPS (void)
{
AT91F_PS_EnablePeriphClock(
AT91C_BASE_PS, // PIO controller base address
((unsigned int) 1 << AT91C_ID_FIQ) |
((unsigned int) 1 << AT91C_ID_IRQ0) |
((unsigned int) 1 << AT91C_ID_IRQ1) |
((unsigned int) 1 << AT91C_ID_IRQ2));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_CfgPIO
//* \brief Configure PIO controllers to drive AIC signals
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIO, // PIO controller base address
((unsigned int) AT91C_P9_IRQ0 ) |
((unsigned int) AT91C_P12_FIQ ) |
((unsigned int) AT91C_P10_IRQ1 ) |
((unsigned int) AT91C_P11_IRQ2 ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC2_CfgPS
//* \brief Enable Peripheral clock in PMC for TC2
//*----------------------------------------------------------------------------
__inline void AT91F_TC2_CfgPS (void)
{
AT91F_PS_EnablePeriphClock(
AT91C_BASE_PS, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC2));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC1_CfgPS
//* \brief Enable Peripheral clock in PMC for TC1
//*----------------------------------------------------------------------------
__inline void AT91F_TC1_CfgPS (void)
{
AT91F_PS_EnablePeriphClock(
AT91C_BASE_PS, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC1));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC0_CfgPS
//* \brief Enable Peripheral clock in PMC for TC0
//*----------------------------------------------------------------------------
__inline void AT91F_TC0_CfgPS (void)
{
AT91F_PS_EnablePeriphClock(
AT91C_BASE_PS, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC0));
}
#endif // lib_AT91R40008_H
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