at91r40008_inc.h

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

#define AT91C_TC0_CCR             (0xFFFE0000) // (TC0) Channel Control Register
#define AT91C_TC0_IMR             (0xFFFE002C) // (TC0) Interrupt Mask Register
#define AT91C_TC0_IER             (0xFFFE0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RC              (0xFFFE001C) // (TC0) Register C
#define AT91C_TC0_RA              (0xFFFE0014) // (TC0) Register A
#define AT91C_TC0_CMR             (0xFFFE0004) // (TC0) Channel Mode Register
// ========== Register definition for TCB0 peripheral ========== 
#define AT91C_TCB0_BCR            (0xFFFE00C0) // (TCB0) TC Block Control Register
#define AT91C_TCB0_BMR            (0xFFFE00C4) // (TCB0) TC Block Mode Register
// ========== Register definition for PDC_US1 peripheral ========== 
#define AT91C_US1_TCR             (0xFFFCC03C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_RCR             (0xFFFCC034) // (PDC_US1) Receive Counter Register
#define AT91C_US1_TPR             (0xFFFCC038) // (PDC_US1) Transmit Pointer Register
#define AT91C_US1_RPR             (0xFFFCC030) // (PDC_US1) Receive Pointer Register
// ========== Register definition for US1 peripheral ========== 
#define AT91C_US1_RTOR            (0xFFFCC024) // (US1) Receiver Time-out Register
#define AT91C_US1_THR             (0xFFFCC01C) // (US1) Transmitter Holding Register
#define AT91C_US1_CSR             (0xFFFCC014) // (US1) Channel Status Register
#define AT91C_US1_IDR             (0xFFFCC00C) // (US1) Interrupt Disable Register
#define AT91C_US1_MR              (0xFFFCC004) // (US1) Mode Register
#define AT91C_US1_TTGR            (0xFFFCC028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_BRGR            (0xFFFCC020) // (US1) Baud Rate Generator Register
#define AT91C_US1_RHR             (0xFFFCC018) // (US1) Receiver Holding Register
#define AT91C_US1_IMR             (0xFFFCC010) // (US1) Interrupt Mask Register
#define AT91C_US1_IER             (0xFFFCC008) // (US1) Interrupt Enable Register
#define AT91C_US1_CR              (0xFFFCC000) // (US1) Control Register
// ========== Register definition for PDC_US0 peripheral ========== 
#define AT91C_US0_TCR             (0xFFFD003C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_RCR             (0xFFFD0034) // (PDC_US0) Receive Counter Register
#define AT91C_US0_TPR             (0xFFFD0038) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_RPR             (0xFFFD0030) // (PDC_US0) Receive Pointer Register
// ========== Register definition for US0 peripheral ========== 
#define AT91C_US0_RTOR            (0xFFFD0024) // (US0) Receiver Time-out Register
#define AT91C_US0_THR             (0xFFFD001C) // (US0) Transmitter Holding Register
#define AT91C_US0_CSR             (0xFFFD0014) // (US0) Channel Status Register
#define AT91C_US0_IDR             (0xFFFD000C) // (US0) Interrupt Disable Register
#define AT91C_US0_MR              (0xFFFD0004) // (US0) Mode Register
#define AT91C_US0_TTGR            (0xFFFD0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_BRGR            (0xFFFD0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_RHR             (0xFFFD0018) // (US0) Receiver Holding Register
#define AT91C_US0_IMR             (0xFFFD0010) // (US0) Interrupt Mask Register
#define AT91C_US0_IER             (0xFFFD0008) // (US0) Interrupt Enable Register
#define AT91C_US0_CR              (0xFFFD0000) // (US0) Control Register
// ========== Register definition for SF peripheral ========== 
#define AT91C_SF_PMR              (0xFFF00018) // (SF) Protect Mode Register
#define AT91C_SF_RSR              (0xFFF00008) // (SF) Reset Status Register
#define AT91C_SF_CIDR             (0xFFF00000) // (SF) Chip ID Register
#define AT91C_SF_MMR              (0xFFF0000C) // (SF) Memory Mode Register
#define AT91C_SF_EXID             (0xFFF00004) // (SF) Chip ID Extension Register
// ========== Register definition for EBI peripheral ========== 
#define AT91C_EBI_RCR             (0xFFE00020) // (EBI) Remap Control Register
#define AT91C_EBI_CSR             (0xFFE00000) // (EBI) Chip-select Register
#define AT91C_EBI_MCR             (0xFFE00024) // (EBI) Memory Control Register

// *****************************************************************************
//               PIO DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_PIO_P0              (1 <<  0) // Pin Controlled by P0
#define AT91C_P0_TCLK0            (AT91C_PIO_P0) //  Timer 0 Clock signal
#define AT91C_PIO_P1              (1 <<  1) // Pin Controlled by P1
#define AT91C_P1_TIOA0            (AT91C_PIO_P1) //  Timer 0 Signal A
#define AT91C_PIO_P10             (1 << 10) // Pin Controlled by P10
#define AT91C_P10_IRQ1            (AT91C_PIO_P10) //  External Interrupt 1
#define AT91C_PIO_P11             (1 << 11) // Pin Controlled by P11
#define AT91C_P11_IRQ2            (AT91C_PIO_P11) //  External Interrupt 2
#define AT91C_PIO_P12             (1 << 12) // Pin Controlled by P12
#define AT91C_P12_FIQ             (AT91C_PIO_P12) //  Fast External Interrupt
#define AT91C_PIO_P13             (1 << 13) // Pin Controlled by P13
#define AT91C_P13_SCK0            (AT91C_PIO_P13) //  USART 0 Serial Clock
#define AT91C_PIO_P14             (1 << 14) // Pin Controlled by P14
#define AT91C_P14_TXD0            (AT91C_PIO_P14) //  USART 0 Transmit Data
#define AT91C_PIO_P15             (1 << 15) // Pin Controlled by P15
#define AT91C_P15_RXD0            (AT91C_PIO_P15) //  USART 0 Receive Data
#define AT91C_PIO_P16             (1 << 16) // Pin Controlled by P16
#define AT91C_PIO_P17             (1 << 17) // Pin Controlled by P17
#define AT91C_PIO_P18             (1 << 18) // Pin Controlled by P18
#define AT91C_PIO_P19             (1 << 19) // Pin Controlled by P19
#define AT91C_PIO_P2              (1 <<  2) // Pin Controlled by P2
#define AT91C_P2_TIOB0            (AT91C_PIO_P2) //  Timer 0 Signal B
#define AT91C_PIO_P20             (1 << 20) // Pin Controlled by P20
#define AT91C_P20_SCK1            (AT91C_PIO_P20) //  USART 1 Serial Clock
#define AT91C_PIO_P21             (1 << 21) // Pin Controlled by P21
#define AT91C_P21_TXD1            (AT91C_PIO_P21) //  USART 1 Transmit Data
#define AT91C_P21_NTRI            (AT91C_PIO_P21) //  Tri-state Mode
#define AT91C_PIO_P22             (1 << 22) // Pin Controlled by P22
#define AT91C_P22_RXD1            (AT91C_PIO_P22) //  USART 1 Receive Data
#define AT91C_PIO_P23             (1 << 23) // Pin Controlled by P23
#define AT91C_PIO_P24             (1 << 24) // Pin Controlled by P24
#define AT91C_P24_BMS             (AT91C_PIO_P24) //  Boot Mode Select
#define AT91C_PIO_P25             (1 << 25) // Pin Controlled by P25
#define AT91C_P25_MCKO            (AT91C_PIO_P25) //  Master Clock Out
#define AT91C_PIO_P26             (1 << 26) // Pin Controlled by P26
#define AT91C_P26_NCS2            (AT91C_PIO_P26) //  Chip Select 2
#define AT91C_PIO_P27             (1 << 27) // Pin Controlled by P27
#define AT91C_P27_NCS3            (AT91C_PIO_P27) //  Chip Select 3
#define AT91C_PIO_P28             (1 << 28) // Pin Controlled by P28
#define AT91C_P28_A20             (AT91C_PIO_P28) //  Address line A20
#define AT91C_P28_NCS7            (AT91C_PIO_P28) //  Chip Select 7
#define AT91C_PIO_P29             (1 << 29) // Pin Controlled by P29
#define AT91C_P29_A21             (AT91C_PIO_P29) //  Address line A21
#define AT91C_P29_NCS6            (AT91C_PIO_P29) //  Chip Select 6
#define AT91C_PIO_P3              (1 <<  3) // Pin Controlled by P3
#define AT91C_P3_TCLK1            (AT91C_PIO_P3) //  Timer 1 Clock signal
#define AT91C_PIO_P30             (1 << 30) // Pin Controlled by P30
#define AT91C_P30_A22             (AT91C_PIO_P30) //  Address line A22
#define AT91C_P30_NCS5            (AT91C_PIO_P30) //  Chip Select 5
#define AT91C_PIO_P31             (1 << 31) // Pin Controlled by P31
#define AT91C_P31_A23             (AT91C_PIO_P31) //  Address line A23
#define AT91C_P31_NCS4            (AT91C_PIO_P31) //  Chip Select 4
#define AT91C_PIO_P4              (1 <<  4) // Pin Controlled by P4
#define AT91C_P4_TIOA1            (AT91C_PIO_P4) //  Timer 1 Signal A
#define AT91C_PIO_P5              (1 <<  5) // Pin Controlled by P5
#define AT91C_P5_TIOB1            (AT91C_PIO_P5) //  Timer 1 Signal B
#define AT91C_PIO_P6              (1 <<  6) // Pin Controlled by P6
#define AT91C_P6_TCLK2            (AT91C_PIO_P6) //  Timer 2 Clock signal
#define AT91C_PIO_P7              (1 <<  7) // Pin Controlled by P7
#define AT91C_P7_TIOA2            (AT91C_PIO_P7) //  Timer 2 Signal A
#define AT91C_PIO_P8              (1 <<  8) // Pin Controlled by P8
#define AT91C_P8_TIOB2            (AT91C_PIO_P8) //  Timer 2 Signal B
#define AT91C_PIO_P9              (1 <<  9) // Pin Controlled by P9
#define AT91C_P9_IRQ0             (AT91C_PIO_P9) //  External Interrupt 0

// *****************************************************************************
//               PERIPHERAL ID DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS              ( 1) // SWI
#define AT91C_ID_US0              ( 2) // USART 0
#define AT91C_ID_US1              ( 3) // USART 1
#define AT91C_ID_TC0              ( 4) // Timer Counter 0
#define AT91C_ID_TC1              ( 5) // Timer Counter 1
#define AT91C_ID_TC2              ( 6) // Timer Counter 2
#define AT91C_ID_WD               ( 7) // Watchdog Timer
#define AT91C_ID_PIO              ( 8) // Parallel IO Controller
#define AT91C_ID_IRQ0             (16) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1             (17) // Advanced Interrupt Controller (IRQ1)
#define AT91C_ID_IRQ2             (18) // Advanced Interrupt Controller (IRQ2)

// *****************************************************************************
//               BASE ADDRESS DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_WD             (0xFFFF8000) // (WD) Base Address
#define AT91C_BASE_PS             (0xFFFF4000) // (PS) Base Address
#define AT91C_BASE_PIO            (0xFFFF0000) // (PIO) Base Address
#define AT91C_BASE_TC2            (0xFFFE0080) // (TC2) Base Address
#define AT91C_BASE_TC1            (0xFFFE0040) // (TC1) Base Address
#define AT91C_BASE_TC0            (0xFFFE0000) // (TC0) Base Address
#define AT91C_BASE_TCB0           (0xFFFE0000) // (TCB0) Base Address
#define AT91C_BASE_PDC_US1        (0xFFFCC030) // (PDC_US1) Base Address
#define AT91C_BASE_US1            (0xFFFCC000) // (US1) Base Address
#define AT91C_BASE_PDC_US0        (0xFFFD0030) // (PDC_US0) Base Address
#define AT91C_BASE_US0            (0xFFFD0000) // (US0) Base Address
#define AT91C_BASE_SF             (0xFFF00000) // (SF) Base Address
#define AT91C_BASE_EBI            (0xFFE00000) // (EBI) Base Address

// *****************************************************************************
//               MEMORY MAPPING DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_SRAM_BEFORE_REMAP	  (0x00300000) // Internal SRAM before remap base address
#define AT91C_SRAM_BEFORE_REMAP_SIZE	 (0x00040000) // Internal SRAM before remap size in byte (256 Kbyte)
#define AT91C_SRAM_AFTER_REMAP	   (0x00000000) // Internal SRAM after remap base address
#define AT91C_SRAM_AFTER_REMAP_SIZE	 (0x00040000) // Internal SRAM after remap size in byte (256 Kbyte)