📄 at91r40008_inc.h
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// SOFTWARE API DEFINITION FOR Special Function Interface
// *****************************************************************************
// *** Register offset in AT91S_SF structure ***
#define SF_CIDR ( 0) // Chip ID Register
#define SF_EXID ( 4) // Chip ID Extension Register
#define SF_RSR ( 8) // Reset Status Register
#define SF_MMR (12) // Memory Mode Register
#define SF_PMR (24) // Protect Mode Register
// -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register --------
#define AT91C_SF_VERSION (0x1F << 0) // (SF) Version of the chip
#define AT91C_SF_BIT5 (0x1 << 5) // (SF) Hardwired at 0
#define AT91C_SF_BIT6 (0x1 << 6) // (SF) Hardwired at 1
#define AT91C_SF_BIT7 (0x1 << 7) // (SF) Hardwired at 0
#define AT91C_SF_NVPSIZ (0xF << 8) // (SF) Nonvolatile Program Memory Size
#define AT91C_SF_NVPSIZ_NONE (0x0 << 8) // (SF) None
#define AT91C_SF_NVPSIZ_32K (0x3 << 8) // (SF) 32K Bytes
#define AT91C_SF_NVPSIZ_64K (0x5 << 8) // (SF) 64K Bytes
#define AT91C_SF_NVPSIZ_128K (0x7 << 8) // (SF) 128K Bytes
#define AT91C_SF_NVPSIZ_256K (0x11 << 8) // (SF) 256K Bytes
#define AT91C_SF_NVDSIZ (0xF << 12) // (SF) Nonvolatile Data Memory Size
#define AT91C_SF_NVDSIZ_NONE (0x0 << 12) // (SF) None
#define AT91C_SF_VDSIZ (0xF << 16) // (SF) Volatile Data Memory Size
#define AT91C_SF_VDSIZ_NONE (0x0 << 16) // (SF) None
#define AT91C_SF_VDSIZ_1K (0x3 << 16) // (SF) 1K Bytes
#define AT91C_SF_VDSIZ_2K (0x5 << 16) // (SF) 2K Bytes
#define AT91C_SF_VDSIZ_4K (0x7 << 16) // (SF) 4K Bytes
#define AT91C_SF_VDSIZ_8K (0x11 << 16) // (SF) 8K Bytes
#define AT91C_SF_ARCH (0xFF << 20) // (SF) Chip Architecture
#define AT91C_SF_ARCH_AT91x40 (0x28 << 20) // (SF) AT91x40yyy
#define AT91C_SF_ARCH_AT91x55 (0x37 << 20) // (SF) AT91x55yyy
#define AT91C_SF_ARCH_AT91x63 (0x3F << 20) // (SF) AT91x63yyy
#define AT91C_SF_NVPTYP (0x7 << 28) // (SF) Nonvolatile Program Memory Type
#define AT91C_SF_NVPTYP_NVPTYP_M (0x1 << 28) // (SF) 'M' Series or 'F' Series
#define AT91C_SF_NVPTYP_NVPTYP_R (0x4 << 28) // (SF) 'R' Series
#define AT91C_SF_EXT (0x1 << 31) // (SF) Extension Flag
// -------- SF_RSR : (SF Offset: 0x8) Reset Status Information --------
#define AT91C_SF_RESET (0xFF << 0) // (SF) Cause of Reset
#define AT91C_SF_RESET_WD (0x35) // (SF) Internal Watchdog
#define AT91C_SF_RESET_EXT (0x6C) // (SF) External Pin
// -------- SF_MMR : (SF Offset: 0xc) Memory Mode Register --------
#define AT91C_SF_RAMWU (0x1 << 0) // (SF) Internal Extended RAM Write Detection
// -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register --------
#define AT91C_SF_AIC (0x1 << 5) // (SF) AIC Protect Mode Enable
#define AT91C_SF_PMRKEY (0xFFFF << 16) // (SF) Protect Mode Register Key
// *****************************************************************************
// SOFTWARE API DEFINITION FOR External Bus Interface
// *****************************************************************************
// *** Register offset in AT91S_EBI structure ***
#define EBI_CSR ( 0) // Chip-select Register
#define EBI_RCR (32) // Remap Control Register
#define EBI_MCR (36) // Memory Control Register
// -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register --------
#define AT91C_EBI_DBW (0x3 << 0) // (EBI) Data Bus Width
#define AT91C_EBI_DBW_16 (0x1) // (EBI) 16-bit data bus width
#define AT91C_EBI_DBW_8 (0x2) // (EBI) 8-bit data bus width
#define AT91C_EBI_NWS (0x7 << 2) // (EBI) Number of wait states
#define AT91C_EBI_NWS_1 (0x0 << 2) // (EBI) 1 wait state
#define AT91C_EBI_NWS_2 (0x1 << 2) // (EBI) 2 wait state
#define AT91C_EBI_NWS_3 (0x2 << 2) // (EBI) 3 wait state
#define AT91C_EBI_NWS_4 (0x3 << 2) // (EBI) 4 wait state
#define AT91C_EBI_NWS_5 (0x4 << 2) // (EBI) 5 wait state
#define AT91C_EBI_NWS_6 (0x5 << 2) // (EBI) 6 wait state
#define AT91C_EBI_NWS_7 (0x6 << 2) // (EBI) 7 wait state
#define AT91C_EBI_NWS_8 (0x7 << 2) // (EBI) 8 wait state
#define AT91C_EBI_WSE (0x1 << 5) // (EBI) Wait State Enable
#define AT91C_EBI_PAGES (0x3 << 7) // (EBI) Pages Size
#define AT91C_EBI_PAGES_1M (0x0 << 7) // (EBI) 1M Byte
#define AT91C_EBI_PAGES_4M (0x1 << 7) // (EBI) 4M Byte
#define AT91C_EBI_PAGES_16M (0x2 << 7) // (EBI) 16M Byte
#define AT91C_EBI_PAGES_64M (0x3 << 7) // (EBI) 64M Byte
#define AT91C_EBI_TDF (0x7 << 9) // (EBI) Data Float Output Time
#define AT91C_EBI_TDF_0 (0x0 << 9) // (EBI) 1 TDF
#define AT91C_EBI_TDF_1 (0x1 << 9) // (EBI) 2 TDF
#define AT91C_EBI_TDF_2 (0x2 << 9) // (EBI) 3 TDF
#define AT91C_EBI_TDF_3 (0x3 << 9) // (EBI) 4 TDF
#define AT91C_EBI_TDF_4 (0x4 << 9) // (EBI) 5 TDF
#define AT91C_EBI_TDF_5 (0x5 << 9) // (EBI) 6 TDF
#define AT91C_EBI_TDF_6 (0x6 << 9) // (EBI) 7 TDF
#define AT91C_EBI_TDF_7 (0x7 << 9) // (EBI) 8 TDF
#define AT91C_EBI_BAT (0x1 << 12) // (EBI) Byte Access Type
#define AT91C_EBI_CSEN (0x1 << 13) // (EBI) Chip Select Enable
#define AT91C_EBI_BA (0xFFF << 20) // (EBI) Base Address
// -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register --------
#define AT91C_EBI_RCB (0x1 << 0) // (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices.
// -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register --------
#define AT91C_EBI_ALE (0x7 << 0) // (EBI) Address Line Enable
#define AT91C_EBI_ALE_16M (0x0) // (EBI) Valid Address Bits = A20, A21, A22, A23 Max Addressable Space = 16M Bytes Valid Chip Select=None
#define AT91C_EBI_ALE_8M (0x4) // (EBI) Valid Address Bits = A20, A21, A22 Max Addressable Space = 8M Bytes Valid Chip Select = CS4
#define AT91C_EBI_ALE_4M (0x5) // (EBI) Valid Address Bits = A20, A21 Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5
#define AT91C_EBI_ALE_2M (0x6) // (EBI) Valid Address Bits = A20 Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6
#define AT91C_EBI_ALE_1M (0x7) // (EBI) Valid Address Bits = None Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7
#define AT91C_EBI_DRP (0x1 << 4) // (EBI)
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91R40008
// *****************************************************************************
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector egister
#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode egister
#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register
#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register
#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command egister
// ========== Register definition for WD peripheral ==========
#define AT91C_WD_SR (0xFFFF800C) // (WD) Status Register
#define AT91C_WD_CMR (0xFFFF8004) // (WD) Clock Mode Register
#define AT91C_WD_CR (0xFFFF8008) // (WD) Control Register
#define AT91C_WD_OMR (0xFFFF8000) // (WD) Overflow Mode Register
// ========== Register definition for PS peripheral ==========
#define AT91C_PS_PCDR (0xFFFF4008) // (PS) Peripheral Clock Disable Register
#define AT91C_PS_CR (0xFFFF4000) // (PS) Control Register
#define AT91C_PS_PCSR (0xFFFF400C) // (PS) Peripheral Clock Status Register
#define AT91C_PS_PCER (0xFFFF4004) // (PS) Peripheral Clock Enable Register
// ========== Register definition for PIO peripheral ==========
#define AT91C_PIO_IFSR (0xFFFF0028) // (PIO) Input Filter Status Register
#define AT91C_PIO_IFER (0xFFFF0020) // (PIO) Input Filter Enable Register
#define AT91C_PIO_OSR (0xFFFF0018) // (PIO) Output Status Register
#define AT91C_PIO_OER (0xFFFF0010) // (PIO) Output Enable Register
#define AT91C_PIO_PSR (0xFFFF0008) // (PIO) PIO Status Register
#define AT91C_PIO_PDSR (0xFFFF003C) // (PIO) Pin Data Status Register
#define AT91C_PIO_CODR (0xFFFF0034) // (PIO) Clear Output Data Register
#define AT91C_PIO_IFDR (0xFFFF0024) // (PIO) Input Filter Disable Register
#define AT91C_PIO_IMR (0xFFFF0048) // (PIO) Interrupt Mask Register
#define AT91C_PIO_IER (0xFFFF0040) // (PIO) Interrupt Enable Register
#define AT91C_PIO_ODSR (0xFFFF0038) // (PIO) Output Data Status Register
#define AT91C_PIO_SODR (0xFFFF0030) // (PIO) Set Output Data Register
#define AT91C_PIO_PER (0xFFFF0000) // (PIO) PIO Enable Register
#define AT91C_PIO_ISR (0xFFFF004C) // (PIO) Interrupt Status Register
#define AT91C_PIO_IDR (0xFFFF0044) // (PIO) Interrupt Disable Register
#define AT91C_PIO_PDR (0xFFFF0004) // (PIO) PIO Disable Register
#define AT91C_PIO_ODR (0xFFFF0014) // (PIO) Output Disable Registerr
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_IDR (0xFFFE00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_SR (0xFFFE00A0) // (TC2) Status Register
#define AT91C_TC2_RB (0xFFFE0098) // (TC2) Register B
#define AT91C_TC2_CV (0xFFFE0090) // (TC2) Counter Value
#define AT91C_TC2_CCR (0xFFFE0080) // (TC2) Channel Control Register
#define AT91C_TC2_IMR (0xFFFE00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_IER (0xFFFE00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_RC (0xFFFE009C) // (TC2) Register C
#define AT91C_TC2_RA (0xFFFE0094) // (TC2) Register A
#define AT91C_TC2_CMR (0xFFFE0084) // (TC2) Channel Mode Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_IDR (0xFFFE0068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_SR (0xFFFE0060) // (TC1) Status Register
#define AT91C_TC1_RB (0xFFFE0058) // (TC1) Register B
#define AT91C_TC1_CV (0xFFFE0050) // (TC1) Counter Value
#define AT91C_TC1_CCR (0xFFFE0040) // (TC1) Channel Control Register
#define AT91C_TC1_IMR (0xFFFE006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_IER (0xFFFE0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_RC (0xFFFE005C) // (TC1) Register C
#define AT91C_TC1_RA (0xFFFE0054) // (TC1) Register A
#define AT91C_TC1_CMR (0xFFFE0044) // (TC1) Channel Mode Register
// ========== Register definition for TC0 peripheral ==========
#define AT91C_TC0_IDR (0xFFFE0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_SR (0xFFFE0020) // (TC0) Status Register
#define AT91C_TC0_RB (0xFFFE0018) // (TC0) Register B
#define AT91C_TC0_CV (0xFFFE0010) // (TC0) Counter Value
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