at91r40008_inc.h

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

// ----------------------------------------------------------------------------
//          ATMEL Microcontroller Software Support  -  ROUSSET  -
// ----------------------------------------------------------------------------
//  The software is delivered "AS IS" without warranty or condition of any
//  kind, either express, implied or statutory. This includes without
//  limitation any warranty or condition with respect to merchantability or
//  fitness for any particular purpose, or against the infringements of
//  intellectual property rights of others.
// ----------------------------------------------------------------------------
// File Name           : AT91R40008.h
// Object              : AT91R40008 definitions
// Generated           : AT91 SW Application Group  07/02/2003 (12:18:04)
// 
// CVS Reference       : /AT91R40008.pl/1.4/Wed May 28 10:58:50 2003//
// CVS Reference       : /AIC_1246F.pl/1.4/Mon Nov 04 16:50:58 2002//
// CVS Reference       : /WD_1241B.pl/1.1/Mon Nov 04 16:51:00 2002//
// CVS Reference       : /PS_x40.pl/1.2/Tue Nov 12 15:01:50 2002//
// CVS Reference       : /PIO_1321C_x40.pl/1.1/Wed May 28 11:00:32 2003//
// CVS Reference       : /TC_1243B.pl/1.4/Tue Nov 05 11:43:10 2002//
// CVS Reference       : /PDC_1363D.pl/1.3/Wed Oct 23 13:49:46 2002//
// CVS Reference       : /US_1242E.pl/1.5/Thu Nov 21 12:37:56 2002//
// CVS Reference       : /SF_x40.pl/1.1/Tue Nov 12 12:27:20 2002//
// CVS Reference       : /EBI_x40.pl/1.5/Wed Feb 19 08:25:20 2003//
// ----------------------------------------------------------------------------

// Hardware register definition

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
// *****************************************************************************
// *** Register offset in AT91S_AIC structure ***
#define AIC_SMR         ( 0) // Source Mode egister
#define AIC_SVR         (128) // Source Vector egister
#define AIC_IVR         (256) // IRQ Vector Register
#define AIC_FVR         (260) // FIQ Vector Register
#define AIC_ISR         (264) // Interrupt Status Register
#define AIC_IPR         (268) // Interrupt Pending Register
#define AIC_IMR         (272) // Interrupt Mask Register
#define AIC_CISR        (276) // Core Interrupt Status Register
#define AIC_IECR        (288) // Interrupt Enable Command Register
#define AIC_IDCR        (292) // Interrupt Disable Command egister
#define AIC_ICCR        (296) // Interrupt Clear Command Register
#define AIC_ISCR        (300) // Interrupt Set Command Register
#define AIC_EOICR       (304) // End of Interrupt Command Register
#define AIC_SPU         (308) // Spurious Vector Register
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Watchdog Timer Interface
// *****************************************************************************
// *** Register offset in AT91S_WD structure ***
#define WD_OMR          ( 0) // Overflow Mode Register
#define WD_CMR          ( 4) // Clock Mode Register
#define WD_CR           ( 8) // Control Register
#define WD_SR           (12) // Status Register
// -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register -------- 
#define AT91C_WD_WDEN             (0x1 <<  0) // (WD) Watchdog Enable
#define AT91C_WD_RSTEN            (0x1 <<  1) // (WD) Reset Enable
#define AT91C_WD_IRQEN            (0x1 <<  2) // (WD) Interrupt Enable
#define AT91C_WD_EXTEN            (0x1 <<  3) // (WD) External Signal Enable
#define AT91C_WD_OKEY             (0xFFF <<  4) // (WD) Watchdog Enable
// -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register -------- 
#define AT91C_WD_WDCLKS           (0x3 <<  0) // (WD) Clock Selection
#define 	AT91C_WD_WDCLKS_MCK32                (0x0) // (WD) Master Clock divided by 32
#define 	AT91C_WD_WDCLKS_MCK128               (0x1) // (WD) Master Clock divided by 128
#define 	AT91C_WD_WDCLKS_MCK1024              (0x2) // (WD) Master Clock divided by 1024
#define 	AT91C_WD_WDCLKS_MCK4096              (0x3) // (WD) Master Clock divided by 4096
#define AT91C_WD_HPCV             (0xF <<  2) // (WD) High Pre-load Counter Value
#define AT91C_WD_CKEY             (0x1FF <<  7) // (WD) Clock Access Key
// -------- WD_CR : (WD Offset: 0x8) Control Register -------- 
#define AT91C_WD_RSTKEY           (0xFFFF <<  0) // (WD) Restart Key
// -------- WD_SR : (WD Offset: 0xc) Status Register -------- 
#define AT91C_WD_WDOVF            (0x1 <<  0) // (WD) Watchdog Overflow

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Power Saving Controler
// *****************************************************************************
// *** Register offset in AT91S_PS structure ***
#define PS_CR           ( 0) // Control Register
#define PS_PCER         ( 4) // Peripheral Clock Enable Register
#define PS_PCDR         ( 8) // Peripheral Clock Disable Register
#define PS_PCSR         (12) // Peripheral Clock Status Register
// -------- PS_PCER : (PS Offset: 0x4) Peripheral Clock Enable Register -------- 
#define AT91C_PS_US0              (0x1 <<  2) // (PS) Usart 0 Clock
#define AT91C_PS_US1              (0x1 <<  3) // (PS) Usart 1 Clock
#define AT91C_PS_TC0              (0x1 <<  4) // (PS) Timer Counter 0 Clock
#define AT91C_PS_TC1              (0x1 <<  5) // (PS) Timer Counter 1 Clock
#define AT91C_PS_TC2              (0x1 <<  6) // (PS) Timer Counter 2 Clock
#define AT91C_PS_PIO              (0x1 <<  8) // (PS) PIO Clock
// -------- PS_PCDR : (PS Offset: 0x8) Peripheral Clock Disable Register -------- 
// -------- PS_PCSR : (PS Offset: 0xc) Peripheral Clock Satus Register -------- 

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
// *****************************************************************************
// *** Register offset in AT91S_PIO structure ***
#define PIO_PER         ( 0) // PIO Enable Register
#define PIO_PDR         ( 4) // PIO Disable Register
#define PIO_PSR         ( 8) // PIO Status Register
#define PIO_OER         (16) // Output Enable Register
#define PIO_ODR         (20) // Output Disable Registerr
#define PIO_OSR         (24) // Output Status Register
#define PIO_IFER        (32) // Input Filter Enable Register
#define PIO_IFDR        (36) // Input Filter Disable Register
#define PIO_IFSR        (40) // Input Filter Status Register
#define PIO_SODR        (48) // Set Output Data Register
#define PIO_CODR        (52) // Clear Output Data Register
#define PIO_ODSR        (56) // Output Data Status Register
#define PIO_PDSR        (60) // Pin Data Status Register
#define PIO_IER         (64) // Interrupt Enable Register
#define PIO_IDR         (68) // Interrupt Disable Register
#define PIO_IMR         (72) // Interrupt Mask Register
#define PIO_ISR         (76) // Interrupt Status Register

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
// *****************************************************************************
// *** Register offset in AT91S_TC structure ***
#define TC_CCR          ( 0) // Channel Control Register
#define TC_CMR          ( 4) // Channel Mode Register
#define TC_CV           (16) // Counter Value
#define TC_RA           (20) // Register A
#define TC_RB           (24) // Register B
#define TC_RC           (28) // Register C
#define TC_SR           (32) // Status Register
#define TC_IER          (36) // Interrupt Enable Register
#define TC_IDR          (40) // Interrupt Disable Register
#define TC_IMR          (44) // Interrupt Mask Register
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
#define 	AT91C_TC_EEVT_NONE                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define 	AT91C_TC_EEVT_RISING               (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define 	AT91C_TC_EEVT_FALLING              (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define 	AT91C_TC_EEVT_BOTH                 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x1 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define 	AT91C_TC_WAVESEL_UPDOWN               (0x2 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE             (0x1 << 15) // (TC) 
#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set