📄 at91r40008.inc
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AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command egister
;- ========== Register definition for WD peripheral ==========
AT91C_WD_SR EQU (0xFFFF800C) ;- (WD) Status Register
AT91C_WD_CMR EQU (0xFFFF8004) ;- (WD) Clock Mode Register
AT91C_WD_CR EQU (0xFFFF8008) ;- (WD) Control Register
AT91C_WD_OMR EQU (0xFFFF8000) ;- (WD) Overflow Mode Register
;- ========== Register definition for PS peripheral ==========
AT91C_PS_PCDR EQU (0xFFFF4008) ;- (PS) Peripheral Clock Disable Register
AT91C_PS_CR EQU (0xFFFF4000) ;- (PS) Control Register
AT91C_PS_PCSR EQU (0xFFFF400C) ;- (PS) Peripheral Clock Status Register
AT91C_PS_PCER EQU (0xFFFF4004) ;- (PS) Peripheral Clock Enable Register
;- ========== Register definition for PIO peripheral ==========
AT91C_PIO_IFSR EQU (0xFFFF0028) ;- (PIO) Input Filter Status Register
AT91C_PIO_IFER EQU (0xFFFF0020) ;- (PIO) Input Filter Enable Register
AT91C_PIO_OSR EQU (0xFFFF0018) ;- (PIO) Output Status Register
AT91C_PIO_OER EQU (0xFFFF0010) ;- (PIO) Output Enable Register
AT91C_PIO_PSR EQU (0xFFFF0008) ;- (PIO) PIO Status Register
AT91C_PIO_PDSR EQU (0xFFFF003C) ;- (PIO) Pin Data Status Register
AT91C_PIO_CODR EQU (0xFFFF0034) ;- (PIO) Clear Output Data Register
AT91C_PIO_IFDR EQU (0xFFFF0024) ;- (PIO) Input Filter Disable Register
AT91C_PIO_IMR EQU (0xFFFF0048) ;- (PIO) Interrupt Mask Register
AT91C_PIO_IER EQU (0xFFFF0040) ;- (PIO) Interrupt Enable Register
AT91C_PIO_ODSR EQU (0xFFFF0038) ;- (PIO) Output Data Status Register
AT91C_PIO_SODR EQU (0xFFFF0030) ;- (PIO) Set Output Data Register
AT91C_PIO_PER EQU (0xFFFF0000) ;- (PIO) PIO Enable Register
AT91C_PIO_ISR EQU (0xFFFF004C) ;- (PIO) Interrupt Status Register
AT91C_PIO_IDR EQU (0xFFFF0044) ;- (PIO) Interrupt Disable Register
AT91C_PIO_PDR EQU (0xFFFF0004) ;- (PIO) PIO Disable Register
AT91C_PIO_ODR EQU (0xFFFF0014) ;- (PIO) Output Disable Registerr
;- ========== Register definition for TC2 peripheral ==========
AT91C_TC2_IDR EQU (0xFFFE00A8) ;- (TC2) Interrupt Disable Register
AT91C_TC2_SR EQU (0xFFFE00A0) ;- (TC2) Status Register
AT91C_TC2_RB EQU (0xFFFE0098) ;- (TC2) Register B
AT91C_TC2_CV EQU (0xFFFE0090) ;- (TC2) Counter Value
AT91C_TC2_CCR EQU (0xFFFE0080) ;- (TC2) Channel Control Register
AT91C_TC2_IMR EQU (0xFFFE00AC) ;- (TC2) Interrupt Mask Register
AT91C_TC2_IER EQU (0xFFFE00A4) ;- (TC2) Interrupt Enable Register
AT91C_TC2_RC EQU (0xFFFE009C) ;- (TC2) Register C
AT91C_TC2_RA EQU (0xFFFE0094) ;- (TC2) Register A
AT91C_TC2_CMR EQU (0xFFFE0084) ;- (TC2) Channel Mode Register
;- ========== Register definition for TC1 peripheral ==========
AT91C_TC1_IDR EQU (0xFFFE0068) ;- (TC1) Interrupt Disable Register
AT91C_TC1_SR EQU (0xFFFE0060) ;- (TC1) Status Register
AT91C_TC1_RB EQU (0xFFFE0058) ;- (TC1) Register B
AT91C_TC1_CV EQU (0xFFFE0050) ;- (TC1) Counter Value
AT91C_TC1_CCR EQU (0xFFFE0040) ;- (TC1) Channel Control Register
AT91C_TC1_IMR EQU (0xFFFE006C) ;- (TC1) Interrupt Mask Register
AT91C_TC1_IER EQU (0xFFFE0064) ;- (TC1) Interrupt Enable Register
AT91C_TC1_RC EQU (0xFFFE005C) ;- (TC1) Register C
AT91C_TC1_RA EQU (0xFFFE0054) ;- (TC1) Register A
AT91C_TC1_CMR EQU (0xFFFE0044) ;- (TC1) Channel Mode Register
;- ========== Register definition for TC0 peripheral ==========
AT91C_TC0_IDR EQU (0xFFFE0028) ;- (TC0) Interrupt Disable Register
AT91C_TC0_SR EQU (0xFFFE0020) ;- (TC0) Status Register
AT91C_TC0_RB EQU (0xFFFE0018) ;- (TC0) Register B
AT91C_TC0_CV EQU (0xFFFE0010) ;- (TC0) Counter Value
AT91C_TC0_CCR EQU (0xFFFE0000) ;- (TC0) Channel Control Register
AT91C_TC0_IMR EQU (0xFFFE002C) ;- (TC0) Interrupt Mask Register
AT91C_TC0_IER EQU (0xFFFE0024) ;- (TC0) Interrupt Enable Register
AT91C_TC0_RC EQU (0xFFFE001C) ;- (TC0) Register C
AT91C_TC0_RA EQU (0xFFFE0014) ;- (TC0) Register A
AT91C_TC0_CMR EQU (0xFFFE0004) ;- (TC0) Channel Mode Register
;- ========== Register definition for TCB0 peripheral ==========
AT91C_TCB0_BCR EQU (0xFFFE00C0) ;- (TCB0) TC Block Control Register
AT91C_TCB0_BMR EQU (0xFFFE00C4) ;- (TCB0) TC Block Mode Register
;- ========== Register definition for PDC_US1 peripheral ==========
AT91C_US1_TCR EQU (0xFFFCC03C) ;- (PDC_US1) Transmit Counter Register
AT91C_US1_RCR EQU (0xFFFCC034) ;- (PDC_US1) Receive Counter Register
AT91C_US1_TPR EQU (0xFFFCC038) ;- (PDC_US1) Transmit Pointer Register
AT91C_US1_RPR EQU (0xFFFCC030) ;- (PDC_US1) Receive Pointer Register
;- ========== Register definition for US1 peripheral ==========
AT91C_US1_RTOR EQU (0xFFFCC024) ;- (US1) Receiver Time-out Register
AT91C_US1_THR EQU (0xFFFCC01C) ;- (US1) Transmitter Holding Register
AT91C_US1_CSR EQU (0xFFFCC014) ;- (US1) Channel Status Register
AT91C_US1_IDR EQU (0xFFFCC00C) ;- (US1) Interrupt Disable Register
AT91C_US1_MR EQU (0xFFFCC004) ;- (US1) Mode Register
AT91C_US1_TTGR EQU (0xFFFCC028) ;- (US1) Transmitter Time-guard Register
AT91C_US1_BRGR EQU (0xFFFCC020) ;- (US1) Baud Rate Generator Register
AT91C_US1_RHR EQU (0xFFFCC018) ;- (US1) Receiver Holding Register
AT91C_US1_IMR EQU (0xFFFCC010) ;- (US1) Interrupt Mask Register
AT91C_US1_IER EQU (0xFFFCC008) ;- (US1) Interrupt Enable Register
AT91C_US1_CR EQU (0xFFFCC000) ;- (US1) Control Register
;- ========== Register definition for PDC_US0 peripheral ==========
AT91C_US0_TCR EQU (0xFFFD003C) ;- (PDC_US0) Transmit Counter Register
AT91C_US0_RCR EQU (0xFFFD0034) ;- (PDC_US0) Receive Counter Register
AT91C_US0_TPR EQU (0xFFFD0038) ;- (PDC_US0) Transmit Pointer Register
AT91C_US0_RPR EQU (0xFFFD0030) ;- (PDC_US0) Receive Pointer Register
;- ========== Register definition for US0 peripheral ==========
AT91C_US0_RTOR EQU (0xFFFD0024) ;- (US0) Receiver Time-out Register
AT91C_US0_THR EQU (0xFFFD001C) ;- (US0) Transmitter Holding Register
AT91C_US0_CSR EQU (0xFFFD0014) ;- (US0) Channel Status Register
AT91C_US0_IDR EQU (0xFFFD000C) ;- (US0) Interrupt Disable Register
AT91C_US0_MR EQU (0xFFFD0004) ;- (US0) Mode Register
AT91C_US0_TTGR EQU (0xFFFD0028) ;- (US0) Transmitter Time-guard Register
AT91C_US0_BRGR EQU (0xFFFD0020) ;- (US0) Baud Rate Generator Register
AT91C_US0_RHR EQU (0xFFFD0018) ;- (US0) Receiver Holding Register
AT91C_US0_IMR EQU (0xFFFD0010) ;- (US0) Interrupt Mask Register
AT91C_US0_IER EQU (0xFFFD0008) ;- (US0) Interrupt Enable Register
AT91C_US0_CR EQU (0xFFFD0000) ;- (US0) Control Register
;- ========== Register definition for SF peripheral ==========
AT91C_SF_PMR EQU (0xFFF00018) ;- (SF) Protect Mode Register
AT91C_SF_RSR EQU (0xFFF00008) ;- (SF) Reset Status Register
AT91C_SF_CIDR EQU (0xFFF00000) ;- (SF) Chip ID Register
AT91C_SF_MMR EQU (0xFFF0000C) ;- (SF) Memory Mode Register
AT91C_SF_EXID EQU (0xFFF00004) ;- (SF) Chip ID Extension Register
;- ========== Register definition for EBI peripheral ==========
AT91C_EBI_RCR EQU (0xFFE00020) ;- (EBI) Remap Control Register
AT91C_EBI_CSR EQU (0xFFE00000) ;- (EBI) Chip-select Register
AT91C_EBI_MCR EQU (0xFFE00024) ;- (EBI) Memory Control Register
;- *****************************************************************************
;- PIO DEFINITIONS FOR AT91R40008
;- *****************************************************************************
AT91C_PIO_P0 EQU (1:SHL:0) ;- Pin Controlled by P0
AT91C_P0_TCLK0 EQU (AT91C_PIO_P0) ;- Timer 0 Clock signal
AT91C_PIO_P1 EQU (1:SHL:1) ;- Pin Controlled by P1
AT91C_P1_TIOA0 EQU (AT91C_PIO_P1) ;- Timer 0 Signal A
AT91C_PIO_P10 EQU (1:SHL:10) ;- Pin Controlled by P10
AT91C_P10_IRQ1 EQU (AT91C_PIO_P10) ;- External Interrupt 1
AT91C_PIO_P11 EQU (1:SHL:11) ;- Pin Controlled by P11
AT91C_P11_IRQ2 EQU (AT91C_PIO_P11) ;- External Interrupt 2
AT91C_PIO_P12 EQU (1:SHL:12) ;- Pin Controlled by P12
AT91C_P12_FIQ EQU (AT91C_PIO_P12) ;- Fast External Interrupt
AT91C_PIO_P13 EQU (1:SHL:13) ;- Pin Controlled by P13
AT91C_P13_SCK0 EQU (AT91C_PIO_P13) ;- USART 0 Serial Clock
AT91C_PIO_P14 EQU (1:SHL:14) ;- Pin Controlled by P14
AT91C_P14_TXD0 EQU (AT91C_PIO_P14) ;- USART 0 Transmit Data
AT91C_PIO_P15 EQU (1:SHL:15) ;- Pin Controlled by P15
AT91C_P15_RXD0 EQU (AT91C_PIO_P15) ;- USART 0 Receive Data
AT91C_PIO_P16 EQU (1:SHL:16) ;- Pin Controlled by P16
AT91C_PIO_P17 EQU (1:SHL:17) ;- Pin Controlled by P17
AT91C_PIO_P18 EQU (1:SHL:18) ;- Pin Controlled by P18
AT91C_PIO_P19 EQU (1:SHL:19) ;- Pin Controlled by P19
AT91C_PIO_P2 EQU (1:SHL:2) ;- Pin Controlled by P2
AT91C_P2_TIOB0 EQU (AT91C_PIO_P2) ;- Timer 0 Signal B
AT91C_PIO_P20 EQU (1:SHL:20) ;- Pin Controlled by P20
AT91C_P20_SCK1 EQU (AT91C_PIO_P20) ;- USART 1 Serial Clock
AT91C_PIO_P21 EQU (1:SHL:21) ;- Pin Controlled by P21
AT91C_P21_TXD1 EQU (AT91C_PIO_P21) ;- USART 1 Transmit Data
AT91C_P21_NTRI EQU (AT91C_PIO_P21) ;- Tri-state Mode
AT91C_PIO_P22 EQU (1:SHL:22) ;- Pin Controlled by P22
AT91C_P22_RXD1 EQU (AT91C_PIO_P22) ;- USART 1 Receive Data
AT91C_PIO_P23 EQU (1:SHL:23) ;- Pin Controlled by P23
AT91C_PIO_P24 EQU (1:SHL:24) ;- Pin Controlled by P24
AT91C_P24_BMS EQU (AT91C_PIO_P24) ;- Boot Mode Select
AT91C_PIO_P25 EQU (1:SHL:25) ;- Pin Controlled by P25
AT91C_P25_MCKO EQU (AT91C_PIO_P25) ;- Master Clock Out
AT91C_PIO_P26 EQU (1:SHL:26) ;- Pin Controlled by P26
AT91C_P26_NCS2 EQU (AT91C_PIO_P26) ;- Chip Select 2
AT91C_PIO_P27 EQU (1:SHL:27) ;- Pin Controlled by P27
AT91C_P27_NCS3 EQU (AT91C_PIO_P27) ;- Chip Select 3
AT91C_PIO_P28 EQU (1:SHL:28) ;- Pin Controlled by P28
AT91C_P28_A20 EQU (AT91C_PIO_P28) ;- Address line A20
AT91C_P28_NCS7 EQU (AT91C_PIO_P28) ;- Chip Select 7
AT91C_PIO_P29 EQU (1:SHL:29) ;- Pin Controlled by P29
AT91C_P29_A21 EQU (AT91C_PIO_P29) ;- Address line A21
AT91C_P29_NCS6 EQU (AT91C_PIO_P29) ;- Chip Select 6
AT91C_PIO_P3 EQU (1:SHL:3) ;- Pin Controlled by P3
AT91C_P3_TCLK1 EQU (AT91C_PIO_P3) ;- Timer 1 Clock signal
AT91C_PIO_P30 EQU (1:SHL:30) ;- Pin Controlled by P30
AT91C_P30_A22 EQU (AT91C_PIO_P30) ;- Address line A22
AT91C_P30_NCS5 EQU (AT91C_PIO_P30) ;- Chip Select 5
AT91C_PIO_P31 EQU (1:SHL:31) ;- Pin Controlled by P31
AT91C_P31_A23 EQU (AT91C_PIO_P31) ;- Address line A23
AT91C_P31_NCS4 EQU (AT91C_PIO_P31) ;- Chip Select 4
AT91C_PIO_P4 EQU (1:SHL:4) ;- Pin Controlled by P4
AT91C_P4_TIOA1 EQU (AT91C_PIO_P4) ;- Timer 1 Signal A
AT91C_PIO_P5 EQU (1:SHL:5) ;- Pin Controlled by P5
AT91C_P5_TIOB1 EQU (AT91C_PIO_P5) ;- Timer 1 Signal B
AT91C_PIO_P6 EQU (1:SHL:6) ;- Pin Controlled by P6
AT91C_P6_TCLK2 EQU (AT91C_PIO_P6) ;- Timer 2 Clock signal
AT91C_PIO_P7 EQU (1:SHL:7) ;- Pin Controlled by P7
AT91C_P7_TIOA2 EQU (AT91C_PIO_P7) ;- Timer 2 Signal A
AT91C_PIO_P8 EQU (1:SHL:8) ;- Pin Controlled by P8
AT91C_P8_TIOB2 EQU (AT91C_PIO_P8) ;- Timer 2 Signal B
AT91C_PIO_P9 EQU (1:SHL:9) ;- Pin Controlled by P9
AT91C_P9_IRQ0 EQU (AT91C_PIO_P9) ;- External Interrupt 0
;- *****************************************************************************
;- PERIPHERAL ID DEFINITIONS FOR AT91R40008
;- *****************************************************************************
AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
AT91C_ID_SYS EQU ( 1) ;- SWI
AT91C_ID_US0 EQU ( 2) ;- USART 0
AT91C_ID_US1 EQU ( 3) ;- USART 1
AT91C_ID_TC0 EQU ( 4) ;- Timer Counter 0
AT91C_ID_TC1 EQU ( 5) ;- Timer Counter 1
AT91C_ID_TC2 EQU ( 6) ;- Timer Counter 2
AT91C_ID_WD EQU ( 7) ;- Watchdog Timer
AT91C_ID_PIO EQU ( 8) ;- Parallel IO Controller
AT91C_ID_IRQ0 EQU (16) ;- Advanced Interrupt Controller (IRQ0)
AT91C_ID_IRQ1 EQU (17) ;- Advanced Interrupt Controller (IRQ1)
AT91C_ID_IRQ2 EQU (18) ;- Advanced Interrupt Controller (IRQ2)
;- *****************************************************************************
;- BASE ADDRESS DEFINITIONS FOR AT91R40008
;- *****************************************************************************
AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address
AT91C_BASE_WD EQU (0xFFFF8000) ;- (WD) Base Address
AT91C_BASE_PS EQU (0xFFFF4000) ;- (PS) Base Address
AT91C_BASE_PIO EQU (0xFFFF0000) ;- (PIO) Base Address
AT91C_BASE_TC2 EQU (0xFFFE0080) ;- (TC2) Base Address
AT91C_BASE_TC1 EQU (0xFFFE0040) ;- (TC1) Base Address
AT91C_BASE_TC0 EQU (0xFFFE0000) ;- (TC0) Base Address
AT91C_BASE_TCB0 EQU (0xFFFE0000) ;- (TCB0) Base Address
AT91C_BASE_PDC_US1 EQU (0xFFFCC030) ;- (PDC_US1) Base Address
AT91C_BASE_US1 EQU (0xFFFCC000) ;- (US1) Base Address
AT91C_BASE_PDC_US0 EQU (0xFFFD0030) ;- (PDC_US0) Base Address
AT91C_BASE_US0 EQU (0xFFFD0000) ;- (US0) Base Address
AT91C_BASE_SF EQU (0xFFF00000) ;- (SF) Base Address
AT91C_BASE_EBI EQU (0xFFE00000) ;- (EBI) Base Address
;- *****************************************************************************
;- MEMORY MAPPING DEFINITIONS FOR AT91R40008
;- *****************************************************************************
AT91C_SRAM_BEFORE_REMAP EQU (0x00300000) ;- Internal SRAM before remap base address
AT91C_SRAM_BEFORE_REMAP_SIZE EQU (0x00040000) ;- Internal SRAM before remap size in byte (256 Kbyte)
AT91C_SRAM_AFTER_REMAP EQU (0x00000000) ;- Internal SRAM after remap base address
AT91C_SRAM_AFTER_REMAP_SIZE EQU (0x00040000) ;- Internal SRAM after remap size in byte (256 Kbyte)
END
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