at91r40008.inc

ARM入门的好帮手.包含了从简单到相对较复杂的程序.

;-              SOFTWARE API DEFINITION  FOR Timer Counter Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_TCB
TCB_TC0         # 48 ;- TC Channel 0
                # 16 ;- Reserved
TCB_TC1         # 48 ;- TC Channel 1
                # 16 ;- Reserved
TCB_TC2         # 48 ;- TC Channel 2
                # 16 ;- Reserved
TCB_BCR         #  4 ;- TC Block Control Register
TCB_BMR         #  4 ;- TC Block Mode Register
;- -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
AT91C_TCB_SYNC            EQU (0x1:SHL:0) ;- (TCB) Synchro Command
;- -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
AT91C_TCB_TC0XC0S         EQU (0x1:SHL:0) ;- (TCB) External Clock Signal 0 Selection
AT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0
AT91C_TCB_TC0XC0S_NONE    EQU (0x1) ;- (TCB) None signal connected to XC0
AT91C_TCB_TC0XC0S_TIOA1   EQU (0x2) ;- (TCB) TIOA1 connected to XC0
AT91C_TCB_TC0XC0S_TIOA2   EQU (0x3) ;- (TCB) TIOA2 connected to XC0
AT91C_TCB_TC1XC1S         EQU (0x1:SHL:2) ;- (TCB) External Clock Signal 1 Selection
AT91C_TCB_TC1XC1S_TCLK1   EQU (0x0:SHL:2) ;- (TCB) TCLK1 connected to XC1
AT91C_TCB_TC1XC1S_NONE    EQU (0x1:SHL:2) ;- (TCB) None signal connected to XC1
AT91C_TCB_TC1XC1S_TIOA0   EQU (0x2:SHL:2) ;- (TCB) TIOA0 connected to XC1
AT91C_TCB_TC1XC1S_TIOA2   EQU (0x3:SHL:2) ;- (TCB) TIOA2 connected to XC1
AT91C_TCB_TC2XC2S         EQU (0x1:SHL:4) ;- (TCB) External Clock Signal 2 Selection
AT91C_TCB_TC2XC2S_TCLK2   EQU (0x0:SHL:4) ;- (TCB) TCLK2 connected to XC2
AT91C_TCB_TC2XC2S_NONE    EQU (0x1:SHL:4) ;- (TCB) None signal connected to XC2
AT91C_TCB_TC2XC2S_TIOA0   EQU (0x2:SHL:4) ;- (TCB) TIOA0 connected to XC2
AT91C_TCB_TC2XC2S_TIOA2   EQU (0x3:SHL:4) ;- (TCB) TIOA2 connected to XC2

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
;- *****************************************************************************
                ^ 0 ;- AT91S_PDC
PDC_RPR         #  4 ;- Receive Pointer Register
PDC_RCR         #  4 ;- Receive Counter Register
PDC_TPR         #  4 ;- Transmit Pointer Register
PDC_TCR         #  4 ;- Transmit Counter Register

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Usart
;- *****************************************************************************
                ^ 0 ;- AT91S_USART
US_CR           #  4 ;- Control Register
US_MR           #  4 ;- Mode Register
US_IER          #  4 ;- Interrupt Enable Register
US_IDR          #  4 ;- Interrupt Disable Register
US_IMR          #  4 ;- Interrupt Mask Register
US_CSR          #  4 ;- Channel Status Register
US_RHR          #  4 ;- Receiver Holding Register
US_THR          #  4 ;- Transmitter Holding Register
US_BRGR         #  4 ;- Baud Rate Generator Register
US_RTOR         #  4 ;- Receiver Time-out Register
US_TTGR         #  4 ;- Transmitter Time-guard Register
                #  4 ;- Reserved
US_RPR          #  4 ;- Receive Pointer Register
US_RCR          #  4 ;- Receive Counter Register
US_TPR          #  4 ;- Transmit Pointer Register
US_TCR          #  4 ;- Transmit Counter Register
;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
AT91C_US_RSTRX            EQU (0x1:SHL:2) ;- (USART) Reset Receiver
AT91C_US_RSTTX            EQU (0x1:SHL:3) ;- (USART) Reset Transmitter
AT91C_US_RXEN             EQU (0x1:SHL:4) ;- (USART) Receiver Enable
AT91C_US_RXDIS            EQU (0x1:SHL:5) ;- (USART) Receiver Disable
AT91C_US_TXEN             EQU (0x1:SHL:6) ;- (USART) Transmitter Enable
AT91C_US_TXDIS            EQU (0x1:SHL:7) ;- (USART) Transmitter Disable
AT91C_US_RSTSTA           EQU (0x1:SHL:8) ;- (USART) Reset Status Bits
AT91C_US_STTBRK           EQU (0x1:SHL:9) ;- (USART) Start Break
AT91C_US_STPBRK           EQU (0x1:SHL:10) ;- (USART) Stop Break
AT91C_US_STTTO            EQU (0x1:SHL:11) ;- (USART) Start Time-out
AT91C_US_SENDA            EQU (0x1:SHL:12) ;- (USART) Send Address
;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
AT91C_US_CLKS             EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
AT91C_US_CLKS_CLOCK       EQU (0x0:SHL:4) ;- (USART) Clock
AT91C_US_CLKS_FDIV1       EQU (0x1:SHL:4) ;- (USART) fdiv1
AT91C_US_CLKS_SLOW        EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM)
AT91C_US_CLKS_EXT         EQU (0x3:SHL:4) ;- (USART) External (SCK)
AT91C_US_CHRL             EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
AT91C_US_CHRL_5_BITS      EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits
AT91C_US_CHRL_6_BITS      EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits
AT91C_US_CHRL_7_BITS      EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits
AT91C_US_CHRL_8_BITS      EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits
AT91C_US_SYNC             EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select
AT91C_US_PAR              EQU (0x7:SHL:9) ;- (USART) Parity type
AT91C_US_PAR_EVEN         EQU (0x0:SHL:9) ;- (USART) Even Parity
AT91C_US_PAR_ODD          EQU (0x1:SHL:9) ;- (USART) Odd Parity
AT91C_US_PAR_SPACE        EQU (0x2:SHL:9) ;- (USART) Parity forced to 0 (Space)
AT91C_US_PAR_MARK         EQU (0x3:SHL:9) ;- (USART) Parity forced to 1 (Mark)
AT91C_US_PAR_NONE         EQU (0x4:SHL:9) ;- (USART) No Parity
AT91C_US_PAR_MULTI_DROP   EQU (0x6:SHL:9) ;- (USART) Multi-drop mode
AT91C_US_NBSTOP           EQU (0x3:SHL:12) ;- (USART) Number of Stop bits
AT91C_US_NBSTOP_1_BIT     EQU (0x0:SHL:12) ;- (USART) 1 stop bit
AT91C_US_NBSTOP_15_BIT    EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
AT91C_US_NBSTOP_2_BIT     EQU (0x2:SHL:12) ;- (USART) 2 stop bits
AT91C_US_CHMODE           EQU (0x3:SHL:14) ;- (USART) Channel Mode
AT91C_US_CHMODE_NORMAL    EQU (0x0:SHL:14) ;- (USART) Normal Mode: The USART channel operates as an RX/TX USART.
AT91C_US_CHMODE_AUTO      EQU (0x1:SHL:14) ;- (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.
AT91C_US_CHMODE_LOCAL     EQU (0x2:SHL:14) ;- (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
AT91C_US_CHMODE_REMOTE    EQU (0x3:SHL:14) ;- (USART) Remote Loopback: RXD pin is internally connected to TXD pin.
AT91C_US_MODE9            EQU (0x1:SHL:17) ;- (USART) 9-bit Character length
AT91C_US_CKLO             EQU (0x1:SHL:18) ;- (USART) Clock Output Select
;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
AT91C_US_RXRDY            EQU (0x1:SHL:0) ;- (USART) RXRDY Interrupt
AT91C_US_TXRDY            EQU (0x1:SHL:1) ;- (USART) TXRDY Interrupt
AT91C_US_RXBRK            EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break
AT91C_US_ENDRX            EQU (0x1:SHL:3) ;- (USART) End of Receive Transfer Interrupt
AT91C_US_ENDTX            EQU (0x1:SHL:4) ;- (USART) End of Transmit Interrupt
AT91C_US_OVRE             EQU (0x1:SHL:5) ;- (USART) Overrun Interrupt
AT91C_US_FRAME            EQU (0x1:SHL:6) ;- (USART) Framing Error Interrupt
AT91C_US_PARE             EQU (0x1:SHL:7) ;- (USART) Parity Error Interrupt
AT91C_US_TIMEOUT          EQU (0x1:SHL:8) ;- (USART) Receiver Time-out
AT91C_US_TXEMPTY          EQU (0x1:SHL:9) ;- (USART) TXEMPTY Interrupt
;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Special Function Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_SF
SF_CIDR         #  4 ;- Chip ID Register
SF_EXID         #  4 ;- Chip ID Extension Register
SF_RSR          #  4 ;- Reset Status Register
SF_MMR          #  4 ;- Memory Mode Register
                #  8 ;- Reserved
SF_PMR          #  4 ;- Protect Mode Register
;- -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register -------- 
AT91C_SF_VERSION          EQU (0x1F:SHL:0) ;- (SF) Version of the chip
AT91C_SF_BIT5             EQU (0x1:SHL:5) ;- (SF) Hardwired at 0
AT91C_SF_BIT6             EQU (0x1:SHL:6) ;- (SF) Hardwired at 1
AT91C_SF_BIT7             EQU (0x1:SHL:7) ;- (SF) Hardwired at 0
AT91C_SF_NVPSIZ           EQU (0xF:SHL:8) ;- (SF) Nonvolatile Program Memory Size
AT91C_SF_NVPSIZ_NONE      EQU (0x0:SHL:8) ;- (SF) None
AT91C_SF_NVPSIZ_32K       EQU (0x3:SHL:8) ;- (SF) 32K Bytes
AT91C_SF_NVPSIZ_64K       EQU (0x5:SHL:8) ;- (SF) 64K Bytes
AT91C_SF_NVPSIZ_128K      EQU (0x7:SHL:8) ;- (SF) 128K Bytes
AT91C_SF_NVPSIZ_256K      EQU (0x11:SHL:8) ;- (SF) 256K Bytes
AT91C_SF_NVDSIZ           EQU (0xF:SHL:12) ;- (SF) Nonvolatile Data Memory Size
AT91C_SF_NVDSIZ_NONE      EQU (0x0:SHL:12) ;- (SF) None
AT91C_SF_VDSIZ            EQU (0xF:SHL:16) ;- (SF) Volatile Data Memory Size
AT91C_SF_VDSIZ_NONE       EQU (0x0:SHL:16) ;- (SF) None
AT91C_SF_VDSIZ_1K         EQU (0x3:SHL:16) ;- (SF) 1K Bytes
AT91C_SF_VDSIZ_2K         EQU (0x5:SHL:16) ;- (SF) 2K Bytes
AT91C_SF_VDSIZ_4K         EQU (0x7:SHL:16) ;- (SF) 4K Bytes
AT91C_SF_VDSIZ_8K         EQU (0x11:SHL:16) ;- (SF) 8K Bytes
AT91C_SF_ARCH             EQU (0xFF:SHL:20) ;- (SF) Chip Architecture
AT91C_SF_ARCH_AT91x40     EQU (0x28:SHL:20) ;- (SF) AT91x40yyy
AT91C_SF_ARCH_AT91x55     EQU (0x37:SHL:20) ;- (SF) AT91x55yyy
AT91C_SF_ARCH_AT91x63     EQU (0x3F:SHL:20) ;- (SF) AT91x63yyy
AT91C_SF_NVPTYP           EQU (0x7:SHL:28) ;- (SF) Nonvolatile Program Memory Type
AT91C_SF_NVPTYP_NVPTYP_M  EQU (0x1:SHL:28) ;- (SF) 'M' Series or 'F' Series
AT91C_SF_NVPTYP_NVPTYP_R  EQU (0x4:SHL:28) ;- (SF) 'R' Series
AT91C_SF_EXT              EQU (0x1:SHL:31) ;- (SF) Extension Flag
;- -------- SF_RSR : (SF Offset: 0x8) Reset Status Information -------- 
AT91C_SF_RESET            EQU (0xFF:SHL:0) ;- (SF) Cause of Reset
AT91C_SF_RESET_WD         EQU (0x35) ;- (SF) Internal Watchdog
AT91C_SF_RESET_EXT        EQU (0x6C) ;- (SF) External Pin
;- -------- SF_MMR : (SF Offset: 0xc) Memory Mode Register -------- 
AT91C_SF_RAMWU            EQU (0x1:SHL:0) ;- (SF) Internal Extended RAM Write Detection
;- -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register -------- 
AT91C_SF_AIC              EQU (0x1:SHL:5) ;- (SF) AIC Protect Mode Enable
AT91C_SF_PMRKEY           EQU (0xFFFF:SHL:16) ;- (SF) Protect Mode Register Key

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR External Bus Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_EBI
EBI_CSR         # 32 ;- Chip-select Register
EBI_RCR         #  4 ;- Remap Control Register
EBI_MCR         #  4 ;- Memory Control Register
;- -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register -------- 
AT91C_EBI_DBW             EQU (0x3:SHL:0) ;- (EBI) Data Bus Width
AT91C_EBI_DBW_16          EQU (0x1) ;- (EBI) 16-bit data bus width
AT91C_EBI_DBW_8           EQU (0x2) ;- (EBI) 8-bit data bus width
AT91C_EBI_NWS             EQU (0x7:SHL:2) ;- (EBI) Number of wait states
AT91C_EBI_NWS_1           EQU (0x0:SHL:2) ;- (EBI) 1 wait state
AT91C_EBI_NWS_2           EQU (0x1:SHL:2) ;- (EBI) 2 wait state
AT91C_EBI_NWS_3           EQU (0x2:SHL:2) ;- (EBI) 3 wait state
AT91C_EBI_NWS_4           EQU (0x3:SHL:2) ;- (EBI) 4 wait state
AT91C_EBI_NWS_5           EQU (0x4:SHL:2) ;- (EBI) 5 wait state
AT91C_EBI_NWS_6           EQU (0x5:SHL:2) ;- (EBI) 6 wait state
AT91C_EBI_NWS_7           EQU (0x6:SHL:2) ;- (EBI) 7 wait state
AT91C_EBI_NWS_8           EQU (0x7:SHL:2) ;- (EBI) 8 wait state
AT91C_EBI_WSE             EQU (0x1:SHL:5) ;- (EBI) Wait State Enable
AT91C_EBI_PAGES           EQU (0x3:SHL:7) ;- (EBI) Pages Size
AT91C_EBI_PAGES_1M        EQU (0x0:SHL:7) ;- (EBI) 1M Byte
AT91C_EBI_PAGES_4M        EQU (0x1:SHL:7) ;- (EBI) 4M Byte
AT91C_EBI_PAGES_16M       EQU (0x2:SHL:7) ;- (EBI) 16M Byte
AT91C_EBI_PAGES_64M       EQU (0x3:SHL:7) ;- (EBI) 64M Byte
AT91C_EBI_TDF             EQU (0x7:SHL:9) ;- (EBI) Data Float Output Time
AT91C_EBI_TDF_0           EQU (0x0:SHL:9) ;- (EBI) 1 TDF
AT91C_EBI_TDF_1           EQU (0x1:SHL:9) ;- (EBI) 2 TDF
AT91C_EBI_TDF_2           EQU (0x2:SHL:9) ;- (EBI) 3 TDF
AT91C_EBI_TDF_3           EQU (0x3:SHL:9) ;- (EBI) 4 TDF
AT91C_EBI_TDF_4           EQU (0x4:SHL:9) ;- (EBI) 5 TDF
AT91C_EBI_TDF_5           EQU (0x5:SHL:9) ;- (EBI) 6 TDF
AT91C_EBI_TDF_6           EQU (0x6:SHL:9) ;- (EBI) 7 TDF
AT91C_EBI_TDF_7           EQU (0x7:SHL:9) ;- (EBI) 8 TDF
AT91C_EBI_BAT             EQU (0x1:SHL:12) ;- (EBI) Byte Access Type
AT91C_EBI_CSEN            EQU (0x1:SHL:13) ;- (EBI) Chip Select Enable
AT91C_EBI_BA              EQU (0xFFF:SHL:20) ;- (EBI) Base Address
;- -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register -------- 
AT91C_EBI_RCB             EQU (0x1:SHL:0) ;- (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices.
;- -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register -------- 
AT91C_EBI_ALE             EQU (0x7:SHL:0) ;- (EBI) Address Line Enable
AT91C_EBI_ALE_16M         EQU (0x0) ;- (EBI) Valid Address Bits = A20, A21, A22, A23  Max Addressable Space = 16M Bytes Valid Chip Select=None 
AT91C_EBI_ALE_8M          EQU (0x4) ;- (EBI) Valid Address Bits = A20, A21, A22  Max Addressable Space = 8M Bytes Valid Chip Select = CS4 
AT91C_EBI_ALE_4M          EQU (0x5) ;- (EBI) Valid Address Bits = A20, A21  Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5 
AT91C_EBI_ALE_2M          EQU (0x6) ;- (EBI) Valid Address Bits = A20  Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6 
AT91C_EBI_ALE_1M          EQU (0x7) ;- (EBI) Valid Address Bits = None  Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7 
AT91C_EBI_DRP             EQU (0x1:SHL:4) ;- (EBI) 

;- *****************************************************************************
;-               REGISTER ADDRESS DEFINITION FOR AT91R40008
;- *****************************************************************************
;- ========== Register definition for AIC peripheral ========== 
AT91C_AIC_EOICR           EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
AT91C_AIC_ICCR            EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
AT91C_AIC_IECR            EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
AT91C_AIC_SVR             EQU (0xFFFFF080) ;- (AIC) Source Vector egister
AT91C_AIC_SMR             EQU (0xFFFFF000) ;- (AIC) Source Mode egister
AT91C_AIC_SPU             EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
AT91C_AIC_FVR             EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
AT91C_AIC_IVR             EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
AT91C_AIC_ISR             EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
AT91C_AIC_IMR             EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register