📄 at91r40008.inc
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;- ----------------------------------------------------------------------------
;- ATMEL Microcontroller Software Support - ROUSSET -
;- ----------------------------------------------------------------------------
;- The software is delivered "AS IS" without warranty or condition of any
;- kind, either express, implied or statutory. This includes without
;- limitation any warranty or condition with respect to merchantability or
;- fitness for any particular purpose, or against the infringements of
;- intellectual property rights of others.
;- ----------------------------------------------------------------------------
;- File Name : AT91R40008.h
;- Object : AT91R40008 definitions
;- Generated : AT91 SW Application Group 07/02/2003 (12:18:04)
;-
;- CVS Reference : /AT91R40008.pl/1.4/Wed May 28 10:58:50 2003//
;- CVS Reference : /AIC_1246F.pl/1.4/Mon Nov 04 16:50:58 2002//
;- CVS Reference : /WD_1241B.pl/1.1/Mon Nov 04 16:51:00 2002//
;- CVS Reference : /PS_x40.pl/1.2/Tue Nov 12 15:01:50 2002//
;- CVS Reference : /PIO_1321C_x40.pl/1.1/Wed May 28 11:00:32 2003//
;- CVS Reference : /TC_1243B.pl/1.4/Tue Nov 05 11:43:10 2002//
;- CVS Reference : /PDC_1363D.pl/1.3/Wed Oct 23 13:49:46 2002//
;- CVS Reference : /US_1242E.pl/1.5/Thu Nov 21 12:37:56 2002//
;- CVS Reference : /SF_x40.pl/1.1/Tue Nov 12 12:27:20 2002//
;- CVS Reference : /EBI_x40.pl/1.5/Wed Feb 19 08:25:20 2003//
;- ----------------------------------------------------------------------------
;- Hardware register definition
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
;- *****************************************************************************
^ 0 ;- AT91S_AIC
AIC_SMR # 128 ;- Source Mode egister
AIC_SVR # 128 ;- Source Vector egister
AIC_IVR # 4 ;- IRQ Vector Register
AIC_FVR # 4 ;- FIQ Vector Register
AIC_ISR # 4 ;- Interrupt Status Register
AIC_IPR # 4 ;- Interrupt Pending Register
AIC_IMR # 4 ;- Interrupt Mask Register
AIC_CISR # 4 ;- Core Interrupt Status Register
# 8 ;- Reserved
AIC_IECR # 4 ;- Interrupt Enable Command Register
AIC_IDCR # 4 ;- Interrupt Disable Command egister
AIC_ICCR # 4 ;- Interrupt Clear Command Register
AIC_ISCR # 4 ;- Interrupt Set Command Register
AIC_EOICR # 4 ;- End of Interrupt Command Register
AIC_SPU # 4 ;- Spurious Vector Register
;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
AT91C_AIC_PRIOR EQU (0x7:SHL:0) ;- (AIC) Priority Level
AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level
AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level
AT91C_AIC_SRCTYPE EQU (0x3:SHL:5) ;- (AIC) Interrupt Source Type
AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label Level Sensitive
AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Edge triggered
AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) External Sources Code Label High-level Sensitive
AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) External Sources Code Label Positive Edge triggered
;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
AT91C_AIC_NFIQ EQU (0x1:SHL:0) ;- (AIC) NFIQ Status
AT91C_AIC_NIRQ EQU (0x1:SHL:1) ;- (AIC) NIRQ Status
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Watchdog Timer Interface
;- *****************************************************************************
^ 0 ;- AT91S_WD
WD_OMR # 4 ;- Overflow Mode Register
WD_CMR # 4 ;- Clock Mode Register
WD_CR # 4 ;- Control Register
WD_SR # 4 ;- Status Register
;- -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register --------
AT91C_WD_WDEN EQU (0x1:SHL:0) ;- (WD) Watchdog Enable
AT91C_WD_RSTEN EQU (0x1:SHL:1) ;- (WD) Reset Enable
AT91C_WD_IRQEN EQU (0x1:SHL:2) ;- (WD) Interrupt Enable
AT91C_WD_EXTEN EQU (0x1:SHL:3) ;- (WD) External Signal Enable
AT91C_WD_OKEY EQU (0xFFF:SHL:4) ;- (WD) Watchdog Enable
;- -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register --------
AT91C_WD_WDCLKS EQU (0x3:SHL:0) ;- (WD) Clock Selection
AT91C_WD_WDCLKS_MCK32 EQU (0x0) ;- (WD) Master Clock divided by 32
AT91C_WD_WDCLKS_MCK128 EQU (0x1) ;- (WD) Master Clock divided by 128
AT91C_WD_WDCLKS_MCK1024 EQU (0x2) ;- (WD) Master Clock divided by 1024
AT91C_WD_WDCLKS_MCK4096 EQU (0x3) ;- (WD) Master Clock divided by 4096
AT91C_WD_HPCV EQU (0xF:SHL:2) ;- (WD) High Pre-load Counter Value
AT91C_WD_CKEY EQU (0x1FF:SHL:7) ;- (WD) Clock Access Key
;- -------- WD_CR : (WD Offset: 0x8) Control Register --------
AT91C_WD_RSTKEY EQU (0xFFFF:SHL:0) ;- (WD) Restart Key
;- -------- WD_SR : (WD Offset: 0xc) Status Register --------
AT91C_WD_WDOVF EQU (0x1:SHL:0) ;- (WD) Watchdog Overflow
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Power Saving Controler
;- *****************************************************************************
^ 0 ;- AT91S_PS
PS_CR # 4 ;- Control Register
PS_PCER # 4 ;- Peripheral Clock Enable Register
PS_PCDR # 4 ;- Peripheral Clock Disable Register
PS_PCSR # 4 ;- Peripheral Clock Status Register
;- -------- PS_PCER : (PS Offset: 0x4) Peripheral Clock Enable Register --------
AT91C_PS_US0 EQU (0x1:SHL:2) ;- (PS) Usart 0 Clock
AT91C_PS_US1 EQU (0x1:SHL:3) ;- (PS) Usart 1 Clock
AT91C_PS_TC0 EQU (0x1:SHL:4) ;- (PS) Timer Counter 0 Clock
AT91C_PS_TC1 EQU (0x1:SHL:5) ;- (PS) Timer Counter 1 Clock
AT91C_PS_TC2 EQU (0x1:SHL:6) ;- (PS) Timer Counter 2 Clock
AT91C_PS_PIO EQU (0x1:SHL:8) ;- (PS) PIO Clock
;- -------- PS_PCDR : (PS Offset: 0x8) Peripheral Clock Disable Register --------
;- -------- PS_PCSR : (PS Offset: 0xc) Peripheral Clock Satus Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Parallel Input Output Controler
;- *****************************************************************************
^ 0 ;- AT91S_PIO
PIO_PER # 4 ;- PIO Enable Register
PIO_PDR # 4 ;- PIO Disable Register
PIO_PSR # 4 ;- PIO Status Register
# 4 ;- Reserved
PIO_OER # 4 ;- Output Enable Register
PIO_ODR # 4 ;- Output Disable Registerr
PIO_OSR # 4 ;- Output Status Register
# 4 ;- Reserved
PIO_IFER # 4 ;- Input Filter Enable Register
PIO_IFDR # 4 ;- Input Filter Disable Register
PIO_IFSR # 4 ;- Input Filter Status Register
# 4 ;- Reserved
PIO_SODR # 4 ;- Set Output Data Register
PIO_CODR # 4 ;- Clear Output Data Register
PIO_ODSR # 4 ;- Output Data Status Register
PIO_PDSR # 4 ;- Pin Data Status Register
PIO_IER # 4 ;- Interrupt Enable Register
PIO_IDR # 4 ;- Interrupt Disable Register
PIO_IMR # 4 ;- Interrupt Mask Register
PIO_ISR # 4 ;- Interrupt Status Register
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
;- *****************************************************************************
^ 0 ;- AT91S_TC
TC_CCR # 4 ;- Channel Control Register
TC_CMR # 4 ;- Channel Mode Register
# 8 ;- Reserved
TC_CV # 4 ;- Counter Value
TC_RA # 4 ;- Register A
TC_RB # 4 ;- Register B
TC_RC # 4 ;- Register C
TC_SR # 4 ;- Status Register
TC_IER # 4 ;- Interrupt Enable Register
TC_IDR # 4 ;- Interrupt Disable Register
TC_IMR # 4 ;- Interrupt Mask Register
;- -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
AT91C_TC_CLKEN EQU (0x1:SHL:0) ;- (TC) Counter Clock Enable Command
AT91C_TC_CLKDIS EQU (0x1:SHL:1) ;- (TC) Counter Clock Disable Command
AT91C_TC_SWTRG EQU (0x1:SHL:2) ;- (TC) Software Trigger Command
;- -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
AT91C_TC_CPCSTOP EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RC Compare
AT91C_TC_CPCDIS EQU (0x1:SHL:7) ;- (TC) Counter Clock Disable with RC Compare
AT91C_TC_EEVTEDG EQU (0x3:SHL:8) ;- (TC) External Event Edge Selection
AT91C_TC_EEVTEDG_NONE EQU (0x0:SHL:8) ;- (TC) Edge: None
AT91C_TC_EEVTEDG_RISING EQU (0x1:SHL:8) ;- (TC) Edge: rising edge
AT91C_TC_EEVTEDG_FALLING EQU (0x2:SHL:8) ;- (TC) Edge: falling edge
AT91C_TC_EEVTEDG_BOTH EQU (0x3:SHL:8) ;- (TC) Edge: each edge
AT91C_TC_EEVT EQU (0x3:SHL:10) ;- (TC) External Event Selection
AT91C_TC_EEVT_NONE EQU (0x0:SHL:10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
AT91C_TC_EEVT_RISING EQU (0x1:SHL:10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
AT91C_TC_EEVT_FALLING EQU (0x2:SHL:10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
AT91C_TC_EEVT_BOTH EQU (0x3:SHL:10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
AT91C_TC_ENETRG EQU (0x1:SHL:12) ;- (TC) External Event Trigger enable
AT91C_TC_WAVESEL EQU (0x3:SHL:13) ;- (TC) Waveform Selection
AT91C_TC_WAVESEL_UP EQU (0x0:SHL:13) ;- (TC) UP mode without atomatic trigger on RC Compare
AT91C_TC_WAVESEL_UP_AUTO EQU (0x1:SHL:13) ;- (TC) UP mode with automatic trigger on RC Compare
AT91C_TC_WAVESEL_UPDOWN EQU (0x2:SHL:13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3:SHL:13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
AT91C_TC_CPCTRG EQU (0x1:SHL:14) ;- (TC) RC Compare Trigger Enable
AT91C_TC_WAVE EQU (0x1:SHL:15) ;- (TC)
AT91C_TC_ACPA EQU (0x3:SHL:16) ;- (TC) RA Compare Effect on TIOA
AT91C_TC_ACPA_NONE EQU (0x0:SHL:16) ;- (TC) Effect: none
AT91C_TC_ACPA_SET EQU (0x1:SHL:16) ;- (TC) Effect: set
AT91C_TC_ACPA_CLEAR EQU (0x2:SHL:16) ;- (TC) Effect: clear
AT91C_TC_ACPA_TOGGLE EQU (0x3:SHL:16) ;- (TC) Effect: toggle
AT91C_TC_ACPC EQU (0x3:SHL:18) ;- (TC) RC Compare Effect on TIOA
AT91C_TC_ACPC_NONE EQU (0x0:SHL:18) ;- (TC) Effect: none
AT91C_TC_ACPC_SET EQU (0x1:SHL:18) ;- (TC) Effect: set
AT91C_TC_ACPC_CLEAR EQU (0x2:SHL:18) ;- (TC) Effect: clear
AT91C_TC_ACPC_TOGGLE EQU (0x3:SHL:18) ;- (TC) Effect: toggle
AT91C_TC_AEEVT EQU (0x3:SHL:20) ;- (TC) External Event Effect on TIOA
AT91C_TC_AEEVT_NONE EQU (0x0:SHL:20) ;- (TC) Effect: none
AT91C_TC_AEEVT_SET EQU (0x1:SHL:20) ;- (TC) Effect: set
AT91C_TC_AEEVT_CLEAR EQU (0x2:SHL:20) ;- (TC) Effect: clear
AT91C_TC_AEEVT_TOGGLE EQU (0x3:SHL:20) ;- (TC) Effect: toggle
AT91C_TC_ASWTRG EQU (0x3:SHL:22) ;- (TC) Software Trigger Effect on TIOA
AT91C_TC_ASWTRG_NONE EQU (0x0:SHL:22) ;- (TC) Effect: none
AT91C_TC_ASWTRG_SET EQU (0x1:SHL:22) ;- (TC) Effect: set
AT91C_TC_ASWTRG_CLEAR EQU (0x2:SHL:22) ;- (TC) Effect: clear
AT91C_TC_ASWTRG_TOGGLE EQU (0x3:SHL:22) ;- (TC) Effect: toggle
AT91C_TC_BCPB EQU (0x3:SHL:24) ;- (TC) RB Compare Effect on TIOB
AT91C_TC_BCPB_NONE EQU (0x0:SHL:24) ;- (TC) Effect: none
AT91C_TC_BCPB_SET EQU (0x1:SHL:24) ;- (TC) Effect: set
AT91C_TC_BCPB_CLEAR EQU (0x2:SHL:24) ;- (TC) Effect: clear
AT91C_TC_BCPB_TOGGLE EQU (0x3:SHL:24) ;- (TC) Effect: toggle
AT91C_TC_BCPC EQU (0x3:SHL:26) ;- (TC) RC Compare Effect on TIOB
AT91C_TC_BCPC_NONE EQU (0x0:SHL:26) ;- (TC) Effect: none
AT91C_TC_BCPC_SET EQU (0x1:SHL:26) ;- (TC) Effect: set
AT91C_TC_BCPC_CLEAR EQU (0x2:SHL:26) ;- (TC) Effect: clear
AT91C_TC_BCPC_TOGGLE EQU (0x3:SHL:26) ;- (TC) Effect: toggle
AT91C_TC_BEEVT EQU (0x3:SHL:28) ;- (TC) External Event Effect on TIOB
AT91C_TC_BEEVT_NONE EQU (0x0:SHL:28) ;- (TC) Effect: none
AT91C_TC_BEEVT_SET EQU (0x1:SHL:28) ;- (TC) Effect: set
AT91C_TC_BEEVT_CLEAR EQU (0x2:SHL:28) ;- (TC) Effect: clear
AT91C_TC_BEEVT_TOGGLE EQU (0x3:SHL:28) ;- (TC) Effect: toggle
AT91C_TC_BSWTRG EQU (0x3:SHL:30) ;- (TC) Software Trigger Effect on TIOB
AT91C_TC_BSWTRG_NONE EQU (0x0:SHL:30) ;- (TC) Effect: none
AT91C_TC_BSWTRG_SET EQU (0x1:SHL:30) ;- (TC) Effect: set
AT91C_TC_BSWTRG_CLEAR EQU (0x2:SHL:30) ;- (TC) Effect: clear
AT91C_TC_BSWTRG_TOGGLE EQU (0x3:SHL:30) ;- (TC) Effect: toggle
;- -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
AT91C_TC_COVFS EQU (0x1:SHL:0) ;- (TC) Counter Overflow
AT91C_TC_LOVRS EQU (0x1:SHL:1) ;- (TC) Load Overrun
AT91C_TC_CPAS EQU (0x1:SHL:2) ;- (TC) RA Compare
AT91C_TC_CPBS EQU (0x1:SHL:3) ;- (TC) RB Compare
AT91C_TC_CPCS EQU (0x1:SHL:4) ;- (TC) RC Compare
AT91C_TC_LDRAS EQU (0x1:SHL:5) ;- (TC) RA Loading
AT91C_TC_LDRBS EQU (0x1:SHL:6) ;- (TC) RB Loading
AT91C_TC_ETRCS EQU (0x1:SHL:7) ;- (TC) External Trigger
AT91C_TC_ETRGS EQU (0x1:SHL:16) ;- (TC) Clock Enabling
AT91C_TC_MTIOA EQU (0x1:SHL:17) ;- (TC) TIOA Mirror
AT91C_TC_MTIOB EQU (0x1:SHL:18) ;- (TC) TIOA Mirror
;- -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
;- -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
;- -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
;- *****************************************************************************
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