fenpin.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(clk:in std_logic;
     clk1,clk2:out std_logic);
end fenpin;
architecture fp of fenpin is
  signal cp1,cp100:std_logic; 
  signal temp1:integer range 0 to 9;
  signal temp3:integer range 0 to 9;
begin 
    
 p1:process(cp100) 
     begin 
      if(cp100'event and cp100='1')then 
        if temp1=9 then temp1<=0; 
        else temp1<=temp1+1; 
        end if; 
        if temp1<=4 then cp1<='0'; 
        else cp1<='1'; 
        end if; 
      end if; 
      
  end process; 
     clk1<=cp1;
         clk2<=cp100;


 p3:process(clk) 
     begin 
      if(clk'event and clk='1')then 
        if temp3=9 then temp3<=0; 
        else temp3<=temp3+1; 
        end if; 
        if temp3<=4 then cp100<='0'; 
        else cp100<='1'; 
        end if; 
      end if; 
      
  end process; 
end;