fangdou.vhd

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library ieee;
use ieee.std_logic_1164.all;
entity fangdou is 
port (clk,key:in std_logic;
      keyout:out std_logic);
end;
architecture a  of fangdou is
signal cp:std_logic;
signal jsq:integer range 0 to 4;
begin
d: process(clk)
begin 
if (clk'event and clk='1') then 
if key='1' then
if jsq=4  then
 jsq<=jsq;
else
 jsq<=jsq+1;
end if;
else
jsq<=0;
end if;
end if;
end process;

process(jsq)
begin
if jsq=3 then 
cp<='1';
else   
cp<='0';
end if;
keyout<=cp;
end process;
end;