📄 main.rpt
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** OUTPUTS **
Shareable
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
73 115 H FF t 6 3 1 0 24 1 18 alarm (:59)
65 101 G FF t 0 0 0 0 4 10 6 cs0 (|display:p1|:30)
64 99 G FF t 0 0 0 0 4 10 6 cs1 (|display:p1|:29)
63 97 G FF t 0 0 0 0 4 10 6 cs2 (|display:p1|:28)
34 61 D FF t 3 2 1 0 12 1 1 segout0
28 40 C FF t 5 1 1 0 12 1 0 segout1
31 35 C FF t 5 1 1 0 14 1 0 segout2
29 38 C FF t 3 0 1 0 10 1 1 segout3
30 37 C FF t 1 0 1 0 10 0 1 segout4
37 56 D FF t 9 3 1 0 14 1 0 segout5
67 104 G FF t 0 0 0 0 9 0 2 segout6
77 123 H FF t 7 3 1 0 24 1 0 state0 (:46)
48 72 E FF t 3 2 1 0 17 1 0 state1 (:45)
79 125 H FF t 0 0 0 0 10 1 0 state2 (:44)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\wash\wash\main.rpt
main
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(25) 45 C XOR s t 2 1 1 0 9 1 0 |display:p1|~1242~1
- 34 C SOFT s t 0 0 0 0 7 0 1 |display:p1|~1242~2
- 54 D OR2 s t 1 0 1 0 6 1 0 |display:p1|~1266~1
(68) 105 G SOFT s t 0 0 0 0 7 1 0 |display:p1|~1266~2
- 47 C OR2 s t 1 0 1 0 13 1 0 |display:p1|~1278~1
(39) 53 D SOFT s t 0 0 0 0 7 1 0 |display:p1|~1314~1
- 44 C DFFE t 0 0 0 1 4 0 3 |fangdou:g1|jsq2 (|fangdou:g1|:4)
(27) 43 C DFFE t 0 0 0 1 3 0 4 |fangdou:g1|jsq1 (|fangdou:g1|:5)
- 42 C DFFE t 0 0 0 1 4 0 4 |fangdou:g1|jsq0 (|fangdou:g1|:6)
(61) 94 F DFFE t 0 0 0 1 4 0 8 |fangdou:g2|jsq2 (|fangdou:g2|:4)
(58) 91 F DFFE t 0 0 0 1 3 0 9 |fangdou:g2|jsq1 (|fangdou:g2|:5)
(57) 88 F DFFE t 0 0 0 1 4 0 9 |fangdou:g2|jsq0 (|fangdou:g2|:6)
- 41 C DFFE + t 0 0 0 0 4 10 11 |fenpin:f1|cp100 (|fenpin:f1|:4)
- 60 D DFFE t 1 0 1 0 5 0 3 |fenpin:f1|temp13 (|fenpin:f1|:5)
- 50 D DFFE t 0 0 0 0 4 0 4 |fenpin:f1|temp12 (|fenpin:f1|:6)
- 55 D DFFE t 0 0 0 0 5 0 4 |fenpin:f1|temp11 (|fenpin:f1|:7)
- 100 G TFFE t 0 0 0 0 1 0 4 |fenpin:f1|temp10 (|fenpin:f1|:8)
(41) 49 D DFFE t 0 0 0 0 5 4 24 |fenpin:f1|cp1 (|fenpin:f1|:9)
- 36 C DFFE + t 0 0 0 0 4 0 3 |fenpin:f1|temp33 (|fenpin:f1|:10)
(23) 48 C DFFE + t 0 0 0 0 3 0 4 |fenpin:f1|temp32 (|fenpin:f1|:11)
- 39 C DFFE + t 0 0 0 0 4 0 4 |fenpin:f1|temp31 (|fenpin:f1|:12)
(70) 109 G TFFE + t 0 0 0 0 0 0 4 |fenpin:f1|temp30 (|fenpin:f1|:13)
- 81 F DFFE t 1 0 1 0 6 4 35 state22 (:25)
(55) 85 F DFFE t 0 0 0 0 6 3 28 state21 (:26)
- 89 F DFFE t 0 0 0 0 6 2 24 state20 (:27)
(62) 96 F DFFE t 0 0 0 0 5 4 4 snum2 (:28)
(60) 93 F DFFE t 0 0 0 0 6 4 3 snum1 (:29)
- 84 F DFFE t 0 0 0 0 6 3 3 snum0 (:30)
- 33 C TFFE t 0 0 0 0 3 4 34 startstop (:31)
(75) 118 H DFFE t 0 0 0 0 10 4 26 count15 (:32)
(74) 117 H TFFE t 0 0 0 0 10 4 26 count14 (:33)
- 76 E TFFE t 1 0 1 0 10 4 26 count13 (:34)
- 121 H TFFE t 0 0 0 0 8 4 26 count12 (:35)
- 28 B TFFE t 1 0 1 0 8 4 26 count11 (:36)
(49) 73 E DFFE t 1 0 0 0 10 4 26 count10 (:37)
- 78 E DFFE t 0 0 0 0 7 4 3 num5 (:38)
- 71 E DFFE t 0 0 0 0 7 4 3 num4 (:39)
- 68 E DFFE t 0 0 0 0 5 6 4 num3 (:40)
(35) 59 D DFFE t 0 0 0 0 5 6 4 num2 (:41)
- 58 D DFFE t 0 0 0 0 5 6 4 num1 (:42)
(36) 57 D DFFE t 0 0 0 0 5 6 3 num0 (:43)
- 113 H DFFE t 0 0 0 0 4 3 18 count25 (:47)
- 82 F DFFE t 1 0 1 0 17 3 17 count24 (:48)
- 74 E DFFE t 3 0 1 0 17 3 23 count23 (:49)
(52) 80 E DFFE t 5 1 1 0 15 3 23 count22 (:50)
- 90 F TFFE t 1 0 0 0 15 3 23 count21 (:51)
(51) 77 E DFFE t 6 2 1 0 17 3 23 count20 (:52)
- 124 H DFFE t 0 0 0 0 4 2 7 count35 (:53)
- 122 H DFFE t 5 1 1 0 24 2 5 count34 (:54)
(46) 69 E DFFE t 0 0 0 0 3 2 10 count33 (:55)
(45) 67 E TFFE t 0 0 0 0 2 2 10 count32 (:56)
- 79 E TFFE t 0 0 0 0 2 2 10 count31 (:57)
- 66 E TFFE t 0 0 0 0 2 2 12 count30 (:58)
(81) 128 H OR2 t ! 0 0 0 0 7 0 2 :1841
- 110 G XOR s t 4 0 1 0 23 0 1 ~1994~1
- 87 F XOR s t 3 0 1 0 20 0 1 ~1994~2
- 106 G XOR s t 7 3 1 0 21 0 1 ~2003~1
(56) 86 F XOR s t 7 3 1 0 21 0 1 ~2012~1
- 103 G OR2 s t 3 2 1 0 19 0 1 ~2021~1
- 2 A XOR s t 1 0 1 0 15 0 1 ~2021~2
- 116 H SOFT s t 0 0 0 0 19 0 1 ~2021~3
- 114 H OR2 s t 2 2 0 0 13 0 1 ~2138~1
- 108 G OR2 s t 2 0 0 0 14 0 1 ~2147~1
(69) 107 G OR2 s t 1 0 1 0 16 0 1 ~2156~1
- 119 H SOFT s t 0 0 0 0 15 0 1 ~2156~2
- 92 F OR2 s t 1 0 1 0 16 0 1 ~2165~1
(80) 126 H SOFT s t 0 0 0 0 15 0 1 ~2165~2
- 95 F OR2 s t 1 0 1 0 16 0 1 ~2174~1
(76) 120 H SOFT s t 0 0 0 0 15 0 1 ~2174~2
(54) 83 F OR2 s t 1 0 1 0 16 0 1 ~2183~1
- 127 H SOFT s t 0 0 0 0 15 0 1 ~2183~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\wash\wash\main.rpt
main
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+- LC2 ~2021~2
|
| Other LABs fed by signals
| that feed LAB 'A'
LC | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
83 -> - | - - - - - - - - | <-- clk
LC81 -> * | * * - - * * * * | <-- state22
LC85 -> * | * - - - * * * * | <-- state21
LC89 -> * | * - - - - * * * | <-- state20
LC33 -> * | * * - * * * * * | <-- startstop
LC113-> * | * - - - * * * * | <-- count25
LC82 -> * | * - - - * * * * | <-- count24
LC74 -> * | * - - - * * * * | <-- count23
LC80 -> * | * - - - * * * * | <-- count22
LC90 -> * | * - - - * * * * | <-- count21
LC77 -> * | * - - - * * * * | <-- count20
LC124-> * | * - - - - - * * | <-- count35
LC122-> * | * - - - - - * * | <-- count34
LC66 -> * | * - - - - * * * | <-- count30
LC103-> * | * - - - - - - - | <-- ~2021~1
LC116-> * | * - - - - - - - | <-- ~2021~3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\wash\wash\main.rpt
main
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+- LC28 count11
|
| Other LABs fed by signals
| that feed LAB 'B'
LC | | A B C D E F G H | Logic cells that feed LAB 'B':
LC28 -> * | - * - - * * * * | <-- count11
Pin
83 -> - | - - - - - - - - | <-- clk
LC115-> * | - * - - * * * * | <-- alarm
LC49 -> * | - * - * * * - * | <-- |fenpin:f1|cp1
LC81 -> * | * * - - * * * * | <-- state22
LC33 -> * | * * - * * * * * | <-- startstop
LC76 -> * | - * - - * * * * | <-- count13
LC121-> * | - * - - * * * * | <-- count12
LC73 -> * | - * - - * * * * | <-- count10
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\wash\wash\main.rpt
main
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC45 |display:p1|~1242~1
| +--------------------------- LC34 |display:p1|~1242~2
| | +------------------------- LC47 |display:p1|~1278~1
| | | +----------------------- LC44 |fangdou:g1|jsq2
| | | | +--------------------- LC43 |fangdou:g1|jsq1
| | | | | +------------------- LC42 |fangdou:g1|jsq0
| | | | | | +----------------- LC41 |fenpin:f1|cp100
| | | | | | | +--------------- LC36 |fenpin:f1|temp33
| | | | | | | | +------------- LC48 |fenpin:f1|temp32
| | | | | | | | | +----------- LC39 |fenpin:f1|temp31
| | | | | | | | | | +--------- LC40 segout1
| | | | | | | | | | | +------- LC35 segout2
| | | | | | | | | | | | +----- LC38 segout3
| | | | | | | | | | | | | +--- LC37 segout4
| | | | | | | | | | | | | | +- LC33 startstop
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
LC34 -> * - - - - - - - - - - - - - - | - - * - - - - - | <-- |display:p1|~1242~2
LC47 -> - - - - - - - - - - - - * - - | - - * - - - - - | <-- |display:p1|~1278~1
LC44 -> - - - * - * - - - - - - - - * | - - * - - - - - | <-- |fangdou:g1|jsq2
LC43 -> - - - * * * - - - - - - - - * | - - * - - - - - | <-- |fangdou:g1|jsq1
LC42 -> - - - * * * - - - - - - - - * | - - * - - - - - | <-- |fangdou:g1|jsq0
LC41 -> - - - * * * - - - - * * * * - | - - * * - * * - | <-- |fenpin:f1|cp100
LC36 -> - - - - - - * * - * - - - - - | - - * - - - - - | <-- |fenpin:f1|temp33
LC48 -> - - - - - - * * * * - - - - - | - - * - - - - - | <-- |fenpin:f1|temp32
LC39 -> - - - - - - * * * * - - - - - | - - * - - - - - | <-- |fenpin:f1|temp31
LC40 -> - - - - - - - - - - * - - - - | - - * - - - - - | <-- segout1
LC35 -> - - - - - - - - - - - * - - - | - - * - - - - - | <-- segout2
LC38 -> - - * - - - - - - - - - * - - | - - * - - - - - | <-- segout3
Pin
83 -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
11 -> - - - * * * - - - - - - - - - | - - * - - - - - | <-- start
LC101-> * * * - - - - - - - * * * * - | - - * * - - * - | <-- cs0
LC99 -> * * * - - - - - - - * * * * - | - - * * - - * - | <-- cs1
LC97 -> * * * - - - - - - - * * * * - | - - * * - - * - | <-- cs2
LC54 -> - - - - - - - - - - - - - * - | - - * - - - - - | <-- |display:p1|~1266~1
LC105-> - - - - - - - - - - - - - * - | - - * - - - - - | <-- |display:p1|~1266~2
LC109-> - - - - - - * * * * - - - - - | - - * - - - - - | <-- |fenpin:f1|temp30
LC104-> * * - - - - - - - - - - - - - | - - * - - - - - | <-- segout6
LC96 -> * - * - - - - - - - * * - * - | - - * * - - - - | <-- snum2
LC93 -> * - * - - - - - - - * * - * - | - - * * - - - - | <-- snum1
LC84 -> - - * - - - - - - - * * - - - | - - * * - - - - | <-- snum0
LC78 -> * - * - - - - - - - - * - * - | - - * * * - - - | <-- num5
LC71 -> * - * - - - - - - - - * - * - | - - * * * - - - | <-- num4
LC68 -> - * * - - - - - - - * * * - - | - - * * * - * - | <-- num3
LC59 -> - * * - - - - - - - * * * - - | - - * * - - * - | <-- num2
LC58 -> - * * - - - - - - - * * * - - | - - * * - - * - | <-- num1
LC57 -> - - * - - - - - - - * * * - - | - - * * - - * - | <-- num0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\wash\wash\main.rpt
main
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
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