coregen.log

FPGA/CPLD集成开发环境ISE使用详解实例－6

# Xilinx CORE Generator 5.1i
# User = wcheng
# Initializing default project...
# Loading plug-ins...
# Initializing GUI...
SETPROJECT J:\projects\ISE\Arch_wzd_demo
# lockprojectprops=false
# busformat=BusFormatAngleBracket
# designflow=Verilog
# expandedprojectpath=J:\projects\ISE\Arch_wzd_demo
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=Verilog VHDL
# xilinxfamily=Virtex2P
# outputoption=DesignFlow
# overwritefiles=Default
# expandedprojectpath=J:\projects\ISE\Arch_wzd_demo
# Set current Project to J:\projects\ISE\Arch_wzd_demo
END