__projnav.log

来自「FPGA/CPLD集成开发环境ISE使用详解实例－6」· LOG 代码 · 共 98 行

LOG
98 行
字号 
Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - xaw2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - xaw2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - xaw2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - xaw2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - xaw2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - xaw2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Started process "View HDL Source".Release 5.1i - xaw2verilog F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.Completed process "View HDL Source".
Started process "View Verilog Instantiation Template".Completed process "View Verilog Instantiation Template".JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    DCM1.v
No errors or warnings

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File-------------------------------------

Started process "View HDL Source".Release 5.1i - xaw2verilog F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.Completed process "View HDL Source".
Started process "View Verilog Instantiation Template".Completed process "View Verilog Instantiation Template".JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    rocket_IO.v
No errors or warnings

JHDPARSE complete -    0 errors,    0 warnings.

__projnav.log - 源码说明

本页面展示了「FPGA/CPLD集成开发环境ISE使用详解实例－6」中的 __projnav.log 源码文件，采用 LOG 编程语言编写，共 98 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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