arch_wzd_demo.gfl

FPGA/CPLD集成开发环境ISE使用详解实例－6

# XAW : PDCL (jhdparse)
# XAW : PDCL (jhdparse)
# XAW : PDCL (jhdparse)
# XAW : PDCL (jhdparse)
# XAW : PDCL (jhdparse)
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.crp
coregen.prj
coregen.fin
# XAW : PDCL (jhdparse)
# XAW : View Verilog Source
DCM1.v
# Verilog : View Verilog Instantiation Template
automake.err
# XAW : View Verilog Source
rocket_IO.v
# Verilog : View Verilog Instantiation Template
automake.err