coregen.crp

FPGA/CPLD集成开发环境ISE使用详解实例－6

NEWPROJECT j:\projects\ise\arch_wzd_demo
SETPROJECT j:\projects\ise\arch_wzd_demo
SET BusFormat = BusFormatAngleBracket
SET XilinxFamily = Virtex2P
SET FlowVendor = Foundation_iSE
SET DesignFlow = Verilog
SET SimulationOutputProducts = Verilog VHDL
SET LockProjectProps = false