rocket_io.v

FPGA/CPLD集成开发环境ISE使用详解实例－6

// Module rocket_IO
// Generated by Xilinx Architecture Wizard
// Verilog
// Written for synthesis tool: XST
// Xilinx device: xc2vp50-5ff1152

module rocket_IO(CONFIGENABLE, CONFIGIN, ENMCOMMAALIGN, ENPCOMMAALIGN, LOOPBACK, POWERDOWN, REFCLK, REFCLK2, REFCLKSEL, BREFCLK, BREFCLK2, RXN, RXP, RXPOLARITY, RXRESET, RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDATA, TXFORCECRCERR, TXINHIBIT, TXPOLARITY, TXRESET, TXUSRCLK, TXUSRCLK2, CONFIGOUT, RXBUFSTATUS, RXCHARISCOMMA, RXCHARISK, RXCHECKINGCRC, RXCLKCORCNT, RXCOMMADET, RXCRCERR, RXDATA, RXDISPERR, RXLOSSOFSYNC, RXNOTINTABLE, RXREALIGN, RXRECCLK, RXRUNDISP, TXBUFERR, TXKERR, TXN, TXP, TXRUNDISP);

input CONFIGENABLE;
input CONFIGIN;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input [1:0] LOOPBACK;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input BREFCLK;
input BREFCLK2;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input [1:0] TXBYPASS8B10B;
input [1:0] TXCHARDISPMODE;
input [1:0] TXCHARDISPVAL;
input [1:0] TXCHARISK;
input [15:0] TXDATA;
input TXFORCECRCERR;
input TXINHIBIT;
input TXPOLARITY;
input TXRESET;
input TXUSRCLK;
input TXUSRCLK2;

output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output RXCHECKINGCRC;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output RXCRCERR;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;
output TXBUFERR;
output [1:0] TXKERR;
output TXN;
output TXP;
output [1:0] TXRUNDISP;


GT_FIBRE_CHAN_2 FibreChannel(
    .CONFIGENABLE (CONFIGENABLE),
    .CONFIGIN (CONFIGIN),
    .ENMCOMMAALIGN (ENMCOMMAALIGN),
    .ENPCOMMAALIGN (ENPCOMMAALIGN),
    .LOOPBACK (LOOPBACK[1:0]),
    .POWERDOWN (POWERDOWN),
    .REFCLK (REFCLK),
    .REFCLK2 (REFCLK2),
    .REFCLKSEL (REFCLKSEL),
    .BREFCLK (BREFCLK),
    .BREFCLK2 (BREFCLK2),
    .RXN (RXN),
    .RXP (RXP),
    .RXPOLARITY (RXPOLARITY),
    .RXRESET (RXRESET),
    .RXUSRCLK (RXUSRCLK),
    .RXUSRCLK2 (RXUSRCLK2),
    .TXBYPASS8B10B (TXBYPASS8B10B[1:0]),
    .TXCHARDISPMODE (TXCHARDISPMODE[1:0]),
    .TXCHARDISPVAL (TXCHARDISPVAL[1:0]),
    .TXCHARISK (TXCHARISK[1:0]),
    .TXDATA (TXDATA[15:0]),
    .TXFORCECRCERR (TXFORCECRCERR),
    .TXINHIBIT (TXINHIBIT),
    .TXPOLARITY (TXPOLARITY),
    .TXRESET (TXRESET),
    .TXUSRCLK (TXUSRCLK),
    .TXUSRCLK2 (TXUSRCLK2),
    .CONFIGOUT (CONFIGOUT),
    .RXBUFSTATUS (RXBUFSTATUS[1:0]),
    .RXCHARISCOMMA (RXCHARISCOMMA[1:0]),
    .RXCHARISK (RXCHARISK[1:0]),
    .RXCHECKINGCRC (RXCHECKINGCRC),
    .RXCLKCORCNT (RXCLKCORCNT[2:0]),
    .RXCOMMADET (RXCOMMADET),
    .RXCRCERR (RXCRCERR),
    .RXDATA (RXDATA[15:0]),
    .RXDISPERR (RXDISPERR[1:0]),
    .RXLOSSOFSYNC (RXLOSSOFSYNC[1:0]),
    .RXNOTINTABLE (RXNOTINTABLE[1:0]),
    .RXREALIGN (RXREALIGN),
    .RXRECCLK (RXRECCLK),
    .RXRUNDISP (RXRUNDISP[1:0]),
    .TXBUFERR (TXBUFERR),
    .TXKERR (TXKERR[1:0]),
    .TXN (TXN),
    .TXP (TXP),
    .TXRUNDISP (TXRUNDISP[1:0]));
// synthesis attribute ALIGN_COMMA_MSB of FibreChannel is "FALSE"
// synthesis attribute CHAN_BOND_LIMIT of FibreChannel is 1
// synthesis attribute CHAN_BOND_MODE of FibreChannel is "OFF"
// synthesis attribute CHAN_BOND_OFFSET of FibreChannel is 0
// synthesis attribute CHAN_BOND_ONE_SHOT of FibreChannel is "TRUE"
// synthesis attribute CHAN_BOND_SEQ_2_USE of FibreChannel is "FALSE"
// synthesis attribute CHAN_BOND_SEQ_LEN of FibreChannel is 1
// synthesis attribute CHAN_BOND_WAIT of FibreChannel is 7
// synthesis attribute CLK_CORRECT_USE of FibreChannel is "TRUE"
// synthesis attribute CLK_COR_INSERT_IDLE_FLAG of FibreChannel is "FALSE"
// synthesis attribute CLK_COR_KEEP_IDLE of FibreChannel is "FALSE"
// synthesis attribute CLK_COR_REPEAT_WAIT of FibreChannel is 2
// synthesis attribute CLK_COR_SEQ_1_1 of FibreChannel is 00110111100
// synthesis attribute CLK_COR_SEQ_1_2 of FibreChannel is 00010010101
// synthesis attribute CLK_COR_SEQ_1_3 of FibreChannel is 00010110101
// synthesis attribute CLK_COR_SEQ_1_4 of FibreChannel is 00010110101
// synthesis attribute CLK_COR_SEQ_2_USE of FibreChannel is "FALSE"
// synthesis attribute CLK_COR_SEQ_LEN of FibreChannel is 4
// synthesis attribute COMMA_10B_MASK of FibreChannel is 1111111000
// synthesis attribute CRC_END_OF_PKT of FibreChannel is "K29_7"
// synthesis attribute CRC_FORMAT of FibreChannel is "FIBRE_CHAN"
// synthesis attribute CRC_START_OF_PKT of FibreChannel is "K27_7"
// synthesis attribute DEC_MCOMMA_DETECT of FibreChannel is "TRUE"
// synthesis attribute DEC_PCOMMA_DETECT of FibreChannel is "TRUE"
// synthesis attribute DEC_VALID_COMMA_ONLY of FibreChannel is "TRUE"
// synthesis attribute MCOMMA_10B_VALUE of FibreChannel is 1100000000
// synthesis attribute MCOMMA_DETECT of FibreChannel is "TRUE"
// synthesis attribute PCOMMA_10B_VALUE of FibreChannel is 0011111000
// synthesis attribute PCOMMA_DETECT of FibreChannel is "TRUE"
// synthesis attribute RX_BUFFER_USE of FibreChannel is "TRUE"
// synthesis attribute RX_CRC_USE of FibreChannel is "TRUE"
// synthesis attribute RX_DATA_WIDTH of FibreChannel is 2
// synthesis attribute RX_DECODE_USE of FibreChannel is "TRUE"
// synthesis attribute RX_LOSS_OF_SYNC_FSM of FibreChannel is "TRUE"
// synthesis attribute RX_LOS_INVALID_INCR of FibreChannel is 1
// synthesis attribute RX_LOS_THRESHOLD of FibreChannel is 4
// synthesis attribute TERMINATION_IMP of FibreChannel is 50
// synthesis attribute SERDES_10B of FibreChannel is "FALSE"
// synthesis attribute TX_BUFFER_USE of FibreChannel is "TRUE"
// synthesis attribute TX_CRC_FORCE_VALUE of FibreChannel is 11010110
// synthesis attribute TX_CRC_USE of FibreChannel is "TRUE"
// synthesis attribute TX_DATA_WIDTH of FibreChannel is 2
// synthesis attribute TX_DIFF_CTRL of FibreChannel is 500
// synthesis attribute TX_PREEMPHASIS of FibreChannel is 0
// synthesis attribute REF_CLK_V_SEL of FibreChannel is 0
// synthesis translate_off
 defparam FibreChannel.ALIGN_COMMA_MSB="FALSE";
 defparam FibreChannel.CHAN_BOND_LIMIT=1;
 defparam FibreChannel.CHAN_BOND_MODE="OFF";
 defparam FibreChannel.CHAN_BOND_OFFSET=0;
 defparam FibreChannel.CHAN_BOND_ONE_SHOT="TRUE";
 defparam FibreChannel.CHAN_BOND_SEQ_2_USE="FALSE";
 defparam FibreChannel.CHAN_BOND_SEQ_LEN=1;
 defparam FibreChannel.CHAN_BOND_WAIT=7;
 defparam FibreChannel.CLK_CORRECT_USE="TRUE";
 defparam FibreChannel.CLK_COR_INSERT_IDLE_FLAG="FALSE";
 defparam FibreChannel.CLK_COR_KEEP_IDLE="FALSE";
 defparam FibreChannel.CLK_COR_REPEAT_WAIT=2;
 defparam FibreChannel.CLK_COR_SEQ_1_1=00110111100;
 defparam FibreChannel.CLK_COR_SEQ_1_2=00010010101;
 defparam FibreChannel.CLK_COR_SEQ_1_3=00010110101;
 defparam FibreChannel.CLK_COR_SEQ_1_4=00010110101;
 defparam FibreChannel.CLK_COR_SEQ_2_USE="FALSE";
 defparam FibreChannel.CLK_COR_SEQ_LEN=4;
 defparam FibreChannel.COMMA_10B_MASK=1111111000;
 defparam FibreChannel.CRC_END_OF_PKT="K29_7";
 defparam FibreChannel.CRC_FORMAT="FIBRE_CHAN";
 defparam FibreChannel.CRC_START_OF_PKT="K27_7";
 defparam FibreChannel.DEC_MCOMMA_DETECT="TRUE";
 defparam FibreChannel.DEC_PCOMMA_DETECT="TRUE";
 defparam FibreChannel.DEC_VALID_COMMA_ONLY="TRUE";
 defparam FibreChannel.MCOMMA_10B_VALUE=1100000000;
 defparam FibreChannel.MCOMMA_DETECT="TRUE";
 defparam FibreChannel.PCOMMA_10B_VALUE=0011111000;
 defparam FibreChannel.PCOMMA_DETECT="TRUE";
 defparam FibreChannel.RX_BUFFER_USE="TRUE";
 defparam FibreChannel.RX_CRC_USE="TRUE";
 defparam FibreChannel.RX_DATA_WIDTH=2;
 defparam FibreChannel.RX_DECODE_USE="TRUE";
 defparam FibreChannel.RX_LOSS_OF_SYNC_FSM="TRUE";
 defparam FibreChannel.RX_LOS_INVALID_INCR=1;
 defparam FibreChannel.RX_LOS_THRESHOLD=4;
 defparam FibreChannel.TERMINATION_IMP=50;
 defparam FibreChannel.SERDES_10B="FALSE";
 defparam FibreChannel.TX_BUFFER_USE="TRUE";
 defparam FibreChannel.TX_CRC_FORCE_VALUE=11010110;
 defparam FibreChannel.TX_CRC_USE="TRUE";
 defparam FibreChannel.TX_DATA_WIDTH=2;
 defparam FibreChannel.TX_DIFF_CTRL=500;
 defparam FibreChannel.TX_PREEMPHASIS=0;
 defparam FibreChannel.REF_CLK_V_SEL=0;
// synthesis translate_on

endmodule