coregen.prj

FPGA/CPLD集成开发环境ISE使用详解实例－6

#COREGen Project File
#Thu Nov 14 21:14:58 CST 2002
xlnx_PCI32v|Xilinx,\ Inc.|3.0=true
async_fifo_v4_0|Xilinx,\ Inc.|4.0=true
C_DA_FIR_V7_0|Xilinx,\ Inc.|7.0=true
nmi_cpu_fpga_virtex|NMI_Electronics_Ltd.|1.0=true
ncoiqvht|Xilinx,\ Inc.|1.1=true
C_DA_FIR_V6_0|Xilinx,\ Inc.|6.0=false
async_fifo_v3_0|Xilinx,\ Inc.|3.0=false
C_DA_FIR_V5_0|Xilinx,\ Inc.|5.0=false
xen_x3des|inSilicon|1.0=true
gva_300|GV_&_Associates_Inc.|1.0=true
C_DECODE_BINARY_V5_0|Xilinx,\ Inc.|5.0=true
tilab_parser|TILAB|1.0=true
sid_v1_1|Xilinx,\ Inc.|1.1=false
canbus|Sci-worx|1.0=true
C_DECODE_BINARY_V4_0|Xilinx,\ Inc.|4.0=false
mac_v1_1|Xilinx,\ Inc.|1.1=false
C_DECODE_BINARY_V3_0|Xilinx,\ Inc.|3.0=false
C_MUX_SLICE_BUFT_V2_0|Xilinx,\ Inc.|2.0=false
fileversion=4
C_MUX_SLICE_BUFT_V1_0|Xilinx,\ Inc.|1.0=false
C_DECODE_BINARY_V2_0|Xilinx,\ Inc.|2.0=false
crc32|Paxonet_Communications,_Inc.|1.0=true
posphyl3_link_v1_0|Xilinx,\ Inc.|1.0=true
vfft16v2|Xilinx,\ Inc.|2.0=true
busformat=BusFormatAngleBracket
mac_v2_0|Xilinx,\ Inc.|2.0=true
c2901|CAST_Inc.|1.0=true
blkmemsp_v4_0|Xilinx,\ Inc.|4.0=true
vfft1024|Xilinx,\ Inc.|1.0=true
blkmemsp_v3_0|Xilinx,\ Inc.|3.0=false
vfft64v2|Xilinx,\ Inc.|2.0=true
C_ADDSUB_V5_0|Xilinx,\ Inc.|5.0=true
c8250|CAST_Inc.|1.0=true
dividervht|Xilinx,\ Inc.|2.0=true
blkmemdp_v3_1|Xilinx,\ Inc.|3.1=false
C_ADDSUB_V4_0|Xilinx,\ Inc.|4.0=false
C_SHIFT_FD_V3_0|Xilinx,\ Inc.|3.0=false
rs_encoder_v3_0|Xilinx,\ Inc.|3.0=true
gva_290|GV_&_Associates_Inc.|1.0=true
C_REG_FD_V5_0|Xilinx,\ Inc.|5.0=true
mult_gen_v4_0|Xilinx,\ Inc.|4.0=false
cselt_turbo_decoder|TILAB|1.0=true
C_ADDSUB_V3_0|Xilinx,\ Inc.|3.0=false
xlnx_PCI64v|Xilinx,\ Inc.|3.0=true
C_SHIFT_FD_V2_0|Xilinx,\ Inc.|2.0=false
encode_8b10b_v1_0|Xilinx,\ Inc.|1.0=false
C_REG_FD_V4_0|Xilinx,\ Inc.|4.0=false
C_SIN_COS_V3_0|Xilinx,\ Inc.|3.0=false
C_ADDSUB_V2_0|Xilinx,\ Inc.|2.0=false
C_SHIFT_FD_V1_0|Xilinx,\ Inc.|1.0=false
enet_brd|Paxonet_Communications,_Inc.|1.0=true
C_REG_FD_V3_0|Xilinx,\ Inc.|3.0=false
C_SIN_COS_V2_0|Xilinx,\ Inc.|2.0=false
C_ADDSUB_V1_0|Xilinx,\ Inc.|1.0=false
blkmemdp_v4_0|Xilinx,\ Inc.|4.0=true
designflow=Verilog
utsla_143s|Paxonet_Communications,_Inc.|1.0=true
C_DDC_V1_0|Xilinx,\ Inc.|1.0=true
C_BIT_CORRELATOR_V3_0|Xilinx,\ Inc.|3.0=true
blkmemdp_v3_0|Xilinx,\ Inc.|3.0=false
C_BIT_CORRELATOR_V2_0|Xilinx,\ Inc.|2.0=false
corelibraryid=0
applied_ima32|Mindspeed_Technologies,_A_Conexant_Business|1.0=true
xlnx_PCIX64_virtex_e_ii|Xilinx,\ Inc.|5.0=true
C_COMPARE_V4_0|Xilinx,\ Inc.|4.0=false
C_GATE_BIT_V5_0|Xilinx,\ Inc.|5.0=true
kdcm_v2_0|Xilinx,\ Inc.|2.0=true
HDLC32_catalog|Xilinx,\ Inc.|1.0=true
C_COMPARE_V3_0|Xilinx,\ Inc.|3.0=false
C_GATE_BIT_V4_0|Xilinx,\ Inc.|4.0=false
C_COMPARE_V2_0|Xilinx,\ Inc.|2.0=false
C_GATE_BIT_V3_0|Xilinx,\ Inc.|3.0=false
C_DA_1D_DCT_V2_1|Xilinx,\ Inc.|2.1=true
C_COMPARE_V1_0|Xilinx,\ Inc.|1.0=false
C_GATE_BIT_V2_0|Xilinx,\ Inc.|2.0=false
formalverification=None
amphion_adpcm1024|Amphion_Semiconductor|1.0=true
C_GATE_BIT_V1_0|Xilinx,\ Inc.|1.0=false
C_MUX_BIT_V2_0|Xilinx,\ Inc.|2.0=false
vfft256|Xilinx,\ Inc.|1.0=true
cam_v3_0|Xilinx,\ Inc.|3.0=true
C_ACCUM_V5_0|Xilinx,\ Inc.|5.0=true
C_MUX_BIT_V1_0|Xilinx,\ Inc.|1.0=false
C_REG_LD_V1_0|Xilinx,\ Inc.|1.0=false
ADPCM32_catalog|Xilinx,\ Inc.|1.0=true
cselt_convenc|TILAB|1.0=true
overwritefiles=Default
C_ACCUM_V4_0|Xilinx,\ Inc.|4.0=false
C_DA_1D_DCT_V2_0|Xilinx,\ Inc.|2.0=false
utsla|Paxonet_Communications,_Inc.|1.0=true
m8254|Virtual_IP_Group,_Inc|1.0=true
C_DA_1D_DCT_V1_0|Xilinx,\ Inc.|1.0=false
C_DIST_MEM_V4_0|Xilinx,\ Inc.|4.0=false
xapp265|Xilinx,\ Inc.|1.1=true
C_DIST_MEM_V3_0|Xilinx,\ Inc.|3.0=false
C_DIST_MEM_V2_0|Xilinx,\ Inc.|2.0=false
eureka_ep100.xcd|Eureka_Technology|1.0=true
rs_decoder_v3_0|Xilinx,\ Inc.|3.0=true
C_DIST_MEM_V1_0|Xilinx,\ Inc.|1.0=false
c8051|CAST_Inc.|1.0=true
cast_c8051.xcd|CAST_Inc.|1.0=true
c8254|CAST_Inc.|1.0=true
jpegc|BARCO_SILEX|1.0=true
cordic_v1_0|Xilinx,\ Inc.|1.0=true
rs_decoder_v2_0|Xilinx,\ Inc.|2.0=false
c16550|CAST_Inc.|1.0=true
flowvendor=Foundation_iSE
C_SHIFT_RAM_V5_0|Xilinx,\ Inc.|5.0=true
C_SHIFT_RAM_V4_0|Xilinx,\ Inc.|4.0=false
C_GATE_BIT_BUS_V5_0|Xilinx,\ Inc.|5.0=true
lfsr_v2_0|Xilinx,\ Inc.|2.0=true
icoding_turbodec|iCODING_Technology,_Inc.|1.0=true
C_SHIFT_RAM_V3_0|Xilinx,\ Inc.|3.0=false
xf_des|MemecCore|1.0=true
xilinxsubfamily=Virtex2P
C_GATE_BIT_BUS_V4_0|Xilinx,\ Inc.|4.0=false
lfsr_v1_0|Xilinx,\ Inc.|1.0=false
crc10|Paxonet_Communications,_Inc.|1.0=true
C_GATE_BIT_BUS_V3_0|Xilinx,\ Inc.|3.0=false
cselt_viterbid|TILAB|1.0=true
cs1100|Paxonet_Communications,_Inc.|1.0=true
C_GATE_BIT_BUS_V2_0|Xilinx,\ Inc.|2.0=false
jpegbw|BARCO_SILEX|1.0=true
C_DECODE_BINARY_V1_0|Xilinx,\ Inc.|1.0=false
sid_v2_0|Xilinx,\ Inc.|2.0=true
amphion_adpcm256|Amphion_Semiconductor|1.0=true
C_MUX_BUS_V5_0|Xilinx,\ Inc.|5.0=true
outputoption=DesignFlow
C_MUX_BUS_V4_0|Xilinx,\ Inc.|4.0=false
m8237|Virtual_IP_Group,_Inc|1.0=true
ppp8_hdlc|Paxonet_Communications,_Inc.|1.0=true
sync_fifo_v3_0|Xilinx,\ Inc.|3.0=true
xf_rsenc|MemecCore|1.0=true
sync_fifo_v2_0|Xilinx,\ Inc.|2.0=false
nmi_uebx|NMI_Electronics_Ltd.|1.0=true
sync_fifo_v1_0|Xilinx,\ Inc.|1.0=false
ncovht|Xilinx,\ Inc.|1.1=true
mds_hdlc|MemecCore|1.0=true
rs_encoder_v2_0|Xilinx,\ Inc.|2.0=false
cselt_arbiter|TILAB|1.0=true
cldl|Paxonet_Communications,_Inc.|1.0=true
eureka_ep201.xcd|Eureka_Technology|1.0=true
xen_u3_atm_tx|inSilicon|1.0=true
vfft32_v3_0|Xilinx,\ Inc.|3.0=true
xf_rsdec|MemecCore|1.0=true
C_REG_FD_V2_0|Xilinx,\ Inc.|2.0=false
C_REG_FD_V1_0|Xilinx,\ Inc.|1.0=false
HDLC1_catalog|Xilinx,\ Inc.|1.0=true
cselt_int_deint|TILAB|1.0=true
C_TWOS_COMP_V5_0|Xilinx,\ Inc.|5.0=true
y2rgb|Perigee_LLC|1.0=true
lockprojectprops=false
rsde|Amphion_Semiconductor|1.0=true
xen_utopia3t|inSilicon|1.0=true
m8255|Virtual_IP_Group,_Inc|1.0=true
vfft256v2|Xilinx,\ Inc.|2.0=true
vfft64|Xilinx,\ Inc.|1.0=true
delta_ltcg|Deltatec|1.0=true
C_MUX_SLICE_BUFE_V5_0|Xilinx,\ Inc.|5.0=true
xftwsi_ms|MemecCore|1.0=true
amphion_adpcm768|Amphion_Semiconductor|1.0=true
cam_v2_0|Xilinx,\ Inc.|2.0=false
amphion_adpcm512|Amphion_Semiconductor|1.0=true
clas|Paxonet_Communications,_Inc.|1.0=true
taxonomymode=1
cam_v1_0|Xilinx,\ Inc.|1.0=false
C_ACCUM_V3_0|Xilinx,\ Inc.|3.0=false
C_ACCUM_V2_0|Xilinx,\ Inc.|2.0=false
ipsemi_speedrouter|IP_Semiconductors|1.0=true
utma|Paxonet_Communications,_Inc.|1.0=true
C_ACCUM_V1_0|Xilinx,\ Inc.|1.0=false
mds_DVB|MemecCore|1.0=true
magicnumber=-1172307782
xen_utopia3r|inSilicon|1.0=true
vfft1024v2|Xilinx,\ Inc.|2.0=true
C_COUNTER_BINARY_V5_0|Xilinx,\ Inc.|5.0=true
simulationoutputproducts=Verilog VHDL
C_COUNTER_BINARY_V4_0|Xilinx,\ Inc.|4.0=false
c8259a|CAST_Inc.|1.0=true
xlnx_PCI32sII|Xilinx,\ Inc.|3.0=true
C_SHIFT_RAM_V2_0|Xilinx,\ Inc.|2.0=false
derivation_java_processor|Derivation_Systems_Inc|1.0=true
C_COUNTER_BINARY_V3_0|Xilinx,\ Inc.|3.0=false
C_GATE_BUS_V5_0|Xilinx,\ Inc.|5.0=true
C_SHIFT_RAM_V1_0|Xilinx,\ Inc.|1.0=false
xfft1024_v1_0|Xilinx,\ Inc.|1.0=true
C_COUNTER_BINARY_V2_0|Xilinx,\ Inc.|2.0=false
arc32risc|ARC\ Cores|1.0=true
cselt_noisy|TILAB|1.0=true
C_GATE_BUS_V4_0|Xilinx,\ Inc.|4.0=false
C_COUNTER_BINARY_V1_0|Xilinx,\ Inc.|1.0=false
eureka_ep520|Eureka_Technology|1.0=true
C_GATE_BIT_BUS_V1_0|Xilinx,\ Inc.|1.0=false
flexbus4_v1_0|Xilinx,\ Inc.|1.0=true
C_GATE_BUS_V3_0|Xilinx,\ Inc.|3.0=false
C_MEM_SP_BLOCK_V1_0|Xilinx,\ Inc.|1.0=true
C_GATE_BUS_V2_0|Xilinx,\ Inc.|2.0=false
blkmemsp_v3_2|Xilinx,\ Inc.|3.2=false
C_MUX_BUS_V3_0|Xilinx,\ Inc.|3.0=false
C_GATE_BUS_V1_0|Xilinx,\ Inc.|1.0=false
cselt_utopia_tx|TILAB|1.0=true
C_MUX_BUS_V2_0|Xilinx,\ Inc.|2.0=false
c80530r|CAST_Inc.|1.0=true
C_MUX_SLICE_BUFT_V5_0|Xilinx,\ Inc.|5.0=true
gva_250|GV_&_Associates_Inc.|1.0=true
C_MUX_BUS_V1_0|Xilinx,\ Inc.|1.0=false
C_DDS_V4_1|Xilinx,\ Inc.|4.1=true
C_MUX_SLICE_BUFT_V4_0|Xilinx,\ Inc.|4.0=false
c16450|CAST_Inc.|1.0=true
C_DDS_V3_1|Xilinx,\ Inc.|3.1=false
C_MUX_SLICE_BUFT_V3_0|Xilinx,\ Inc.|3.0=false
xlnx_pci64_dk|Xilinx,\ Inc.|1.0=true
cselt_descrambler|TILAB|1.0=true
rapid200|Rapid\ Prototypes,\ Inc.|1.0=true
newlogic_boostlite|NewLogic_Technologies,_Inc.|1.0=true
blkmemsp_v3_1|Xilinx,\ Inc.|3.1=false
sdram|NMI_Electronics_Ltd.|1.0=true
blkmemdp_v3_2|Xilinx,\ Inc.|3.2=false
vfft32_v2_0|Xilinx,\ Inc.|2.0=false
xen_jpeg|inSilicon|1.0=true
C_DDS_V4_0|Xilinx,\ Inc.|4.0=false
decode_8b10b_v4_0|Xilinx,\ Inc.|4.0=true
C_SIN_COS_V4_1|Xilinx,\ Inc.|4.1=true
vfft32_v1_0|Xilinx,\ Inc.|1.0=false
cselt_scrambler|TILAB|1.0=true
decode_8b10b_v3_0|Xilinx,\ Inc.|3.0=false
C_CIC_V3_0|Xilinx,\ Inc.|3.0=true
C_DDS_V3_0|Xilinx,\ Inc.|3.0=false
mult_gen_v3_1|Xilinx,\ Inc.|3.1=false
c2910a_mc|CAST_Inc.|1.0=true
decode_8b10b_v2_0|Xilinx,\ Inc.|2.0=false
C_CIC_V2_0|Xilinx,\ Inc.|2.0=false
tilab_fidct|TILAB|1.0=true
C_SHIFT_FD_V5_0|Xilinx,\ Inc.|5.0=true
rgb2y|Perigee_LLC|1.0=true
C_TWOS_COMP_V4_0|Xilinx,\ Inc.|4.0=false
C_CIC_V1_0|Xilinx,\ Inc.|1.0=false
C_SHIFT_FD_V4_0|Xilinx,\ Inc.|4.0=false
encode_8b10b_v3_0|Xilinx,\ Inc.|3.0=true
mult_gen_v5_0|Xilinx,\ Inc.|5.0=true
C_TWOS_COMP_V3_0|Xilinx,\ Inc.|3.0=false
outputproducts=ImpNetlist;ASYSymbol;VerilogSim;VHDLSim
xdes|inSilicon|1.0=true
nmi_upci|NMI_Electronics_Ltd.|1.0=true
encode_8b10b_v2_0|Xilinx,\ Inc.|2.0=false
C_TWOS_COMP_V2_0|Xilinx,\ Inc.|2.0=false
C_SIN_COS_V4_0|Xilinx,\ Inc.|4.0=false
compact_uart|CAST_Inc.|1.0=true
C_TWOS_COMP_V1_0|Xilinx,\ Inc.|1.0=false
cast_r8051|CAST_Inc.|1.0=true
nmi_cpu_fpga_virtex2|NMI_Electronics_Ltd.|1.0=true
iss_adpcm|Amphion_Semiconductor|1.0=true
mult_vgen_v2_0|Xilinx,\ Inc.|2.0=true
C_MUX_SLICE_BUFE_V4_0|Xilinx,\ Inc.|4.0=false
xlnx_PCI64s2|Xilinx,\ Inc.|3.0=true
mult_vgen_v1_0|Xilinx,\ Inc.|1.0=false
C_MUX_SLICE_BUFE_V3_0|Xilinx,\ Inc.|3.0=false
c80530|CAST_Inc.|1.0=true
C_COMPARE_V5_0|Xilinx,\ Inc.|5.0=true
C_MUX_SLICE_BUFE_V2_0|Xilinx,\ Inc.|2.0=false
reed_sol|Amphion_Semiconductor|1.0=true
C_MUX_SLICE_BUFE_V1_0|Xilinx,\ Inc.|1.0=false
sysonchip_turbodec|SysOnChip,_Inc.|1.0=true
cselt_utopia_rx|TILAB|1.0=true
C_MUX_BIT_V5_0|Xilinx,\ Inc.|5.0=true
C_REG_LD_V5_0|Xilinx,\ Inc.|5.0=true
viterbi_v2_0|Xilinx,\ Inc.|2.0=true
C_MUX_BIT_V4_0|Xilinx,\ Inc.|4.0=false
C_REG_LD_V4_0|Xilinx,\ Inc.|4.0=false
C_DIST_MEM_V5_1|Xilinx,\ Inc.|5.1=true
expandedtaxonomy=/Basic_Elements /Communication_&_Networking /Digital_Signal_Processing /Standard_Bus_Interfaces
viterbi_v1_0|Xilinx,\ Inc.|1.0=false
applied_ima8|Mindspeed_Technologies,_A_Conexant_Business|1.0=true
C_DA_2D_DCT_V2_0|Xilinx,\ Inc.|2.0=true
selectedtaxonomy=/Math_Functions
C_MUX_BIT_V3_0|Xilinx,\ Inc.|3.0=false
C_REG_LD_V3_0|Xilinx,\ Inc.|3.0=false
C_DIST_MEM_V4_1|Xilinx,\ Inc.|4.1=false
gva_270|GV_&_Associates_Inc.|1.0=true
C_REG_LD_V2_0|Xilinx,\ Inc.|2.0=false
tilab_ipcam|TILAB|1.0=true
flip805x|Dolphin_Integration|1.0=true
xilinxfamily=Virtex2P
C_MEM_DP_BLOCK_V1_0|Xilinx,\ Inc.|1.0=true
C_DIST_MEM_V5_0|Xilinx,\ Inc.|5.0=false
convolution_v2_0|Xilinx,\ Inc.|2.0=true
xen_u3_atm_rx|inSilicon|1.0=true
convolution_v1_0|Xilinx,\ Inc.|1.0=false
c8255a|CAST_Inc.|1.0=true
C_MAC_FIR_V1_0|Xilinx,\ Inc.|1.0=true
vfft16|Xilinx,\ Inc.|1.0=true