dcm1_arwz.ucf

FPGA/CPLD集成开发环境ISE使用详解实例－6

# Generated by Xilinx Architecture Wizard
# --- UCF Template Only ---
# Cut and paste these attributes into the project's UCF file, if desired
INST DCM_X4 CLK_FEEDBACK = 1X;
INST DCM_X4 CLKDV_DIVIDE = 2;
INST DCM_X4 CLKFX_DIVIDE = 1;
INST DCM_X4 CLKFX_MULTIPLY = 4;
INST DCM_X4 CLKIN_DIVIDE_BY_2 = FALSE;
INST DCM_X4 CLKIN_PERIOD = 10;
INST DCM_X4 CLKOUT_PHASE_SHIFT = NONE;
INST DCM_X4 DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
INST DCM_X4 DFS_FREQUENCY_MODE = LOW;
INST DCM_X4 DLL_FREQUENCY_MODE = LOW;
INST DCM_X4 DUTY_CYCLE_CORRECTION = TRUE;
INST DCM_X4 PHASE_SHIFT = 0;
INST DCM_X4 STARTUP_WAIT = TRUE;