arch_wzd_demo.npl

来自「FPGA/CPLD集成开发环境ISE使用详解实例－6」· NPL 代码 · 共 21 行

JDF F
// Created by Project Navigator ver 1.0
PROJECT Arch_wzd_demo
DESIGN arch_wzd_demo Normal
DEVFAM virtex2p
DEVFAMTIME 1037277579
DEVICE xc2vp50
DEVICETIME 1037277579
DEVPKG ff1152
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
FLOW XST Verilog
FLOWTIME 1037239641
MODULE DCM1.xaw
MODSTYLE DCM1 Normal
MODULE rocket_IO.xaw
MODSTYLE rocket_IO Normal
[STRATEGY-LIST]
Normal=True