alu.srr

FPGA/CPLD集成开发环境ISE使用详解实例－3

***********************


Path information for path number 1: 
    = Required time:                      1000.000

    - Propagation  time:                  2.800
    = Slack (non-critical) :              997.200

    Starting point:                       outp_s[0] / Q
    Ending point:                         outp_s[7:0] / outp_s[0]
    The start point is clocked by         clk [rising] on pin C
    The end   point is clocked by         clk [rising]

Instance / Net              Pin           Pin               Arrival     Fan
Name               Type     Name          Dir     Delay     Time        Out
---------------------------------------------------------------------------
outp_s[0]          FD       Q             Out     0.000     0.000          
outp_s_c[0]        Net                                                  1  
outp_s_obuf[0]     OBUF     I             In                0.000          
outp_s_obuf[0]     OBUF     O             Out     2.800     2.800          
outp_s[0]          Net                                                  1  
outp_s[7:0]        Port     outp_s[0]     Out               2.800          
===========================================================================




====================================
Detailed Report for Clock: System
====================================



Starting Points with worst slack 
********************************

                                                     Arrival            
Instance        Type     Pin           Net           Time        Slack  
                                                                        
------------------------------------------------------------------------
opcode[2:0]     Port     opcode[0]     opcode[0]     0.000       991.640
opcode[2:0]     Port     opcode[2]     opcode[2]     0.000       991.640
a[7:0]          Port     a[0]          a[0]          0.000       992.861
a[7:0]          Port     a[1]          a[1]          0.000       992.942
b[7:0]          Port     b[0]          b[0]          0.000       992.961
a[7:0]          Port     a[2]          a[2]          0.000       993.023
b[7:0]          Port     b[1]          b[1]          0.000       993.042
a[7:0]          Port     a[3]          a[3]          0.000       993.104
b[7:0]          Port     b[2]          b[2]          0.000       993.123
a[7:0]          Port     a[4]          a[4]          0.000       993.185
========================================================================


Ending Points with worst slack 
******************************

                                               Required            
Instance      Type     Pin     Net             Time         Slack  
                                                                   
-------------------------------------------------------------------
outp_a[7]     LD       D       outp_a_1[7]     998.819      991.640
outp_s[7]     FD       D       outp_a_1[7]     998.819      991.640
outp_a[6]     LD       D       outp_a_1[6]     998.819      991.721
outp_s[6]     FD       D       outp_a_1[6]     998.819      991.721
outp_a[5]     LD       D       outp_a_1[5]     998.819      991.802
outp_s[5]     FD       D       outp_a_1[5]     998.819      991.802
outp_a[4]     LD       D       outp_a_1[4]     998.819      991.883
outp_s[4]     FD       D       outp_a_1[4]     998.819      991.883
outp_a[3]     LD       D       outp_a_1[3]     998.819      991.964
outp_s[3]     FD       D       outp_a_1[3]     998.819      991.964
===================================================================



Worst Paths Information
***********************


Path information for path number 1: 
    - Setup time:                         1.181
    = Required time:                      998.819

    - Propagation  time:                  7.179
    = Slack (critical) :                  991.640

    Starting point:                       opcode[2:0] / opcode[0]
    Ending point:                         outp_a[7] / D
    The start point is clocked by         System [rising]
    The end   point is clocked by         System [rising] on pin G

Instance / Net                          Pin           Pin                Arrival     Fan
Name                        Type        Name          Dir     Delay      Time        Out
----------------------------------------------------------------------------------------
opcode[2:0]                 Port        opcode[0]     In      0.000      0.000          
opcode[0]                   Net                                                      1  
opcode_ibuf[0]              IBUF        I             In                 0.000          
opcode_ibuf[0]              IBUF        O             Out     2.547      2.547          
opcode_c[0]                 Net                                                      18 
NoName_un1_un1_opcode_i     LUT2        I1            In                 2.547          
NoName_un1_un1_opcode_i     LUT2        O             Out     1.085      3.632          
NoName_un1_un1_opcode_i     Net                                                      2  
un1_a_1_cry_0               MUXCY_L     CI            In                 3.632          
un1_a_1_cry_0               MUXCY_L     LO            Out     1.135      4.768          
un1_a_1_cry_0               Net                                                      2  
un1_a_1_cry_1               MUXCY_L     CI            In                 4.768          
un1_a_1_cry_1               MUXCY_L     LO            Out     0.081      4.849          
un1_a_1_cry_1               Net                                                      2  
un1_a_1_cry_2               MUXCY_L     CI            In                 4.849          
un1_a_1_cry_2               MUXCY_L     LO            Out     0.081      4.930          
un1_a_1_cry_2               Net                                                      2  
un1_a_1_cry_3               MUXCY_L     CI            In                 4.930          
un1_a_1_cry_3               MUXCY_L     LO            Out     0.081      5.011          
un1_a_1_cry_3               Net                                                      2  
un1_a_1_cry_4               MUXCY_L     CI            In                 5.011          
un1_a_1_cry_4               MUXCY_L     LO            Out     0.081      5.092          
un1_a_1_cry_4               Net                                                      2  
un1_a_1_cry_5               MUXCY_L     CI            In                 5.092          
un1_a_1_cry_5               MUXCY_L     LO            Out     0.081      5.173          
un1_a_1_cry_5               Net                                                      2  
un1_a_1_cry_6               MUXCY_L     CI            In                 5.173          
un1_a_1_cry_6               MUXCY_L     LO            Out     -0.088     5.085          
un1_a_1_cry_6               Net                                                      1  
un1_a_1_s_7                 XORCY       CI            In                 5.085          
un1_a_1_s_7                 XORCY       O             Out     0.437      5.522          
un1_a_1_s_7                 Net                                                      1  
outp_s_8_am[7]              LUT3        I2            In                 5.522          
outp_s_8_am[7]              LUT3        O             Out     0.917      6.439          
outp_s_8_am[7]              Net                                                      1  
outp_s_8[7]                 MUXF5       I0            In                 6.439          
outp_s_8[7]                 MUXF5       O             Out     0.741      7.179          
outp_a_1[7]                 Net                                                      2  
outp_a[7]                   LD          D             In                 7.179          
========================================================================================




##### END TIMING REPORT #####

---------------------------------------
Resource Usage Report for alu 

Mapping to part: xcv50ecs144-8
Cell usage:
MUXCY_L         7 uses
XORCY           8 uses
MUXF5           8 uses
LD              8 uses
FD              8 uses
GND             1 use
VCC             1 use

I/O primitives:
IBUF           19 uses
OBUF           16 uses

BUFGP          1 use

I/O Register bits:                  8
Register bits not including I/Os:   0 (0%)

Global buffer usage summary
BUFGs + BUFGPs: 1 of 4 (25%)


Mapping Summary:
Total  LUTs: 26 (1%)

Mapper successful!
Process took 2.604 seconds realtime, 2.603 seconds cputime