datachoose.v

来自「dds设计」· Verilog 代码 · 共 21 行

//datachoose.v	 	产生三角波模块   2006-5-2	version:1.0		作者：田世坤
//

module datachoose(clk, data1,data2,data3,en1,en2,en3,dataout);
input clk;
input en1, en2, en3;
input [7:0] data1, data2, data3;
output [7:0] dataout;
reg [7:0] dataout;

always @ (posedge clk)
begin
	case({en3,en2,en1})
		3'b001:	dataout = data1;
		3'b010:	dataout = data2;
		3'b100:	dataout = data3;
		default:	dataout = 7'b0;
	endcase
end

endmodule