control.v

dds设计

//name:control.v       主控模块 	2006-5-1	version:1.0		作者：田世坤
//波形输出主控模块：
//输入：clk：系统时钟(10MHz);	
//		keysignal：按键信号;
//输出：DLedout：发光二极管，八位宽;
//      ensqu:方波使能信号
//      entri:三角波使能信号
//      ensin:正弦波使能信号
//      address: 输出地址，10位宽
//中间变量：C:频率控制字，24位宽
//			length:频率控制字递增量，24位宽

module control(clk2,keysignal,ensqu,entri,ensin,DLedout,address);
	input clk2;
	input [7:0]	keysignal;
	output ensqu, entri, ensin;
	output [7:0] DLedout;
	output [9:0] address;
	reg ensqu, entri, ensin;
	reg [7:0] DLedout;
	reg [9:0] address;
	
	reg [28:0] C, length = 29'b00000000000000000000001101011;
	
	reg [2:0] state_wave;
	parameter square = 3'b001, triangle = 3'b010, sin = 3'b100;  
	reg [2:0]  state_adjust;
	parameter adj1 = 3'b001, adj100 = 3'b010, adj10k = 3'b100;
	
		
	
	always @ (posedge clk2)//状态转换控制
	begin
		if(keysignal[7] == 1)
			begin
				DLedout[7:0] <= 8'b10000000;
				state_wave <= square;
				state_adjust <= adj1;
			end
					
		else 
			case(state_wave)
			3'b001: 
				begin
					if(keysignal[0] == 1)	begin
												state_wave <= triangle;
											end												
					else					begin
												DLedout[2:0] <= 3'b001;												
												//{DLedout[2], DLedout[1], DLedout[0]} <= 3'b001;
												{ensin, entri, ensqu} <= 3'b001;
												state_wave <= square;
											end		
				end
			
			3'b010: begin
						if(keysignal[0] == 1)	begin
													state_wave <= sin;
												end
						else				   	begin
													DLedout[2:0] <= 3'b010;
													//{DLedout[2], DLedout[1], DLedout[0]} <= 3'b010;
													{ensin, entri, ensqu} <= 3'b010;										
													state_wave <= triangle;
												end
					end
			3'b100: begin
						if(keysignal[0] == 1)	begin
													state_wave <= square;
												end
						else					begin													
													DLedout[2:0] <= 3'b100;
													//{DLedout[2], DLedout[1], DLedout[0]} <= 3'b100;
													{ensin, entri, ensqu} <= 3'b100;
													state_wave <= sin;
												end	
					end
			default:	state_wave <= square;
			endcase



			case(state_adjust)
			3'b001: 
				begin
					if(keysignal[1] == 1)	begin
												state_adjust <= adj100;
											end												
					else					begin
												DLedout[5:3] <= 3'b001;
												if(keysignal[2] == 1)
												begin	
													DLedout[6] <= 1'b1;
													length <= length - 29'b00000000000000000000001101011;
												end
												else if(keysignal[3] == 1)
												begin	
													DLedout[6] <= 1'b1;
													length <= length + 29'b00000000000000000000001101011;
												end
												C <= C + length;
												address[9:0] <= C[28:19];
												state_adjust <= adj1;
											end		
				end
			
			3'b010: begin
						if(keysignal[1] == 1)	begin
													state_adjust <= adj10k;
												end
						else				   	begin
													DLedout[5:3] <= 3'b010;
													if(keysignal[2] == 1)
													begin	                                
														DLedout[6] <= 1'b1;
														length <= length - 29'b00000000000000010100111110001;
													end
													else if(keysignal[3] == 1)
													begin	
														DLedout[6] <= 1'b1;
														length <= length + 29'b00000000000000010100111110001;
													end
													C <= C + length;
													address[9:0] <= C[28:19];
													state_adjust <= adj100;
												end
					end
			3'b100: begin
						if(keysignal[1] == 1)	begin
													state_adjust <= adj1;
												end
						else					begin
													DLedout[5:3] <= 3'b100;
													if(keysignal[2] == 1)
													begin							
														DLedout[6] <= 1'b1;			   
														length <= length - 29'b00000000100000110001001001110;
													end
													else if(keysignal[3] == 1)
													begin	
														DLedout[6] <= 1'b1;
														length <= length + 29'b00000000100000110001001001110;
													end
													C <= C + length;
													address[9:0] <= C[28:19];
													state_adjust <= adj10k;
												end	
					end
			default:	state_adjust <= adj1;
			endcase
		end

endmodule