ddsfpga.hif

dds设计

Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1595
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
romlookup
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
romlookup.v
1146548890
7
# storage
db|DDSFPGA.(5).cnf
db|DDSFPGA.(5).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
romlookup:inst4
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|DDSFPGA.(6).cnf
db|DDSFPGA.(6).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
1024.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_88s
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
clock0
clocken0
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
romlookup:inst4|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_88s
# case_insensitive
# source_file
db|altsyncram_88s.tdf
1146565136
6
# storage
db|DDSFPGA.(7).cnf
db|DDSFPGA.(7).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
clocken0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# memory_file {
1024.mif
1146548768
}
# hierarchies {
romlookup:inst4|altsyncram:altsyncram_component|altsyncram_88s:auto_generated
}
# end
# entity
datachoose
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
datachoose.v
1146569962
7
# storage
db|DDSFPGA.(8).cnf
db|DDSFPGA.(8).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
datachoose:inst2
}
# end
# entity
clock_d2
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_d2.v
1146570712
7
# storage
db|DDSFPGA.(1).cnf
db|DDSFPGA.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
clock_d2:inst
}
# end
# entity
squwave
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
squwave.v
1146634376
7
# storage
db|DDSFPGA.(3).cnf
db|DDSFPGA.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
squwave:inst5
}
# end
# entity
triawave
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
triawave.v
1146633554
7
# storage
db|DDSFPGA.(4).cnf
db|DDSFPGA.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
triawave:inst6
}
# end
# entity
control
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
control.v
1146644084
7
# storage
db|DDSFPGA.(2).cnf
db|DDSFPGA.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
square
001
PARAMETER_BIN
USR
triangle
010
PARAMETER_BIN
USR
sin
100
PARAMETER_BIN
USR
adj1
001
PARAMETER_BIN
USR
adj100
010
PARAMETER_BIN
USR
adj10k
100
PARAMETER_BIN
USR
}
# hierarchies {
control:inst1
}
# end
# entity
Key
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
key.v
1146651978
7
# storage
db|DDSFPGA.(9).cnf
db|DDSFPGA.(9).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
n
1000
PARAMETER_UNKNOWN
USR
}
# end
# entity
DDSFPGA
# case_insensitive
# source_file
DDSFPGA.bdf
1146659300
23
# storage
db|DDSFPGA.(0).cnf
db|DDSFPGA.(0).cnf
# hierarchies {
|
}
# end
# entity
Key
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
key.v
1146651978
7
# storage
db|DDSFPGA.(10).cnf
db|DDSFPGA.(10).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
n
10
PARAMETER_UNKNOWN
USR
}
# hierarchies {
Key:inst3
}
# end
# complete