ddsfpga.hier_info

dds设计

clk => scan[16].CLK
keyin[0] => nkeyout~15.DATAB
keyin[0] => reduce_nor~2.IN0
keyin[0] => reduce_or~2.IN0
keyin[1] => nkeyout~14.DATAB
keyin[1] => reduce_nor~2.IN1
keyin[1] => reduce_or~2.IN1
keyin[2] => nkeyout~13.DATAB
keyin[2] => reduce_nor~2.IN2
keyin[2] => reduce_or~2.IN2
keyin[3] => nkeyout~12.DATAB
keyin[3] => reduce_nor~2.IN3
keyin[3] => reduce_or~2.IN3
keyin[4] => nkeyout~11.DATAB
keyin[4] => reduce_nor~2.IN4
keyin[4] => reduce_or~2.IN4
keyin[5] => nkeyout~10.DATAB
keyin[5] => reduce_nor~2.IN5
keyin[5] => reduce_or~2.IN5
keyin[6] => nkeyout~9.DATAB
keyin[6] => reduce_nor~2.IN6
keyin[6] => reduce_or~2.IN6
keyin[7] => nkeyout~8.DATAB
keyin[7] => reduce_nor~2.IN7
keyin[7] => reduce_or~2.IN7
keyout[0] <= nkeyout[0].DB_MAX_OUTPUT_PORT_TYPE
keyout[1] <= nkeyout[1].DB_MAX_OUTPUT_PORT_TYPE
keyout[2] <= nkeyout[2].DB_MAX_OUTPUT_PORT_TYPE
keyout[3] <= nkeyout[3].DB_MAX_OUTPUT_PORT_TYPE
keyout[4] <= nkeyout[4].DB_MAX_OUTPUT_PORT_TYPE
keyout[5] <= nkeyout[5].DB_MAX_OUTPUT_PORT_TYPE
keyout[6] <= nkeyout[6].DB_MAX_OUTPUT_PORT_TYPE
keyout[7] <= nkeyout[7].DB_MAX_OUTPUT_PORT_TYPE


|DDSFPGA|squwave:inst5
clk => qsquare[6]~reg0.CLK
clk => qsquare[5]~reg0.CLK
clk => qsquare[4]~reg0.CLK
clk => qsquare[3]~reg0.CLK
clk => qsquare[2]~reg0.CLK
clk => qsquare[1]~reg0.CLK
clk => qsquare[0]~reg0.CLK
clk => qsquare[7]~reg0.CLK
enable => qsquare~0.OUTPUTSELECT
address[0] => LessThan~0.IN20
address[1] => LessThan~0.IN19
address[2] => LessThan~0.IN18
address[3] => LessThan~0.IN17
address[4] => LessThan~0.IN16
address[5] => LessThan~0.IN15
address[6] => LessThan~0.IN14
address[7] => LessThan~0.IN13
address[8] => LessThan~0.IN12
address[9] => LessThan~0.IN11
qsquare[0] <= qsquare[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qsquare[1] <= qsquare[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qsquare[2] <= qsquare[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qsquare[3] <= qsquare[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qsquare[4] <= qsquare[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qsquare[5] <= qsquare[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qsquare[6] <= qsquare[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qsquare[7] <= qsquare[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DDSFPGA|triawave:inst6
clk => qtriangle[6]~reg0.CLK
clk => qtriangle[5]~reg0.CLK
clk => qtriangle[4]~reg0.CLK
clk => qtriangle[3]~reg0.CLK
clk => qtriangle[2]~reg0.CLK
clk => qtriangle[1]~reg0.CLK
clk => qtriangle[0]~reg0.CLK
clk => qtriangle[7]~reg0.CLK
enable => qtriangle~8.OUTPUTSELECT
enable => qtriangle~9.OUTPUTSELECT
enable => qtriangle~10.OUTPUTSELECT
enable => qtriangle~11.OUTPUTSELECT
enable => qtriangle~12.OUTPUTSELECT
enable => qtriangle~13.OUTPUTSELECT
enable => qtriangle~14.OUTPUTSELECT
enable => qtriangle~15.OUTPUTSELECT
address[0] => LessThan~0.IN20
address[1] => LessThan~0.IN19
address[1] => qtriangle~7.DATAB
address[1] => qtriangle~7.DATAA
address[2] => LessThan~0.IN18
address[2] => qtriangle~6.DATAB
address[2] => qtriangle~6.DATAA
address[3] => LessThan~0.IN17
address[3] => qtriangle~5.DATAB
address[3] => qtriangle~5.DATAA
address[4] => LessThan~0.IN16
address[4] => qtriangle~4.DATAB
address[4] => qtriangle~4.DATAA
address[5] => LessThan~0.IN15
address[5] => qtriangle~3.DATAB
address[5] => qtriangle~3.DATAA
address[6] => LessThan~0.IN14
address[6] => qtriangle~2.DATAB
address[6] => qtriangle~2.DATAA
address[7] => LessThan~0.IN13
address[7] => qtriangle~1.DATAB
address[7] => qtriangle~1.DATAA
address[8] => LessThan~0.IN12
address[8] => qtriangle~0.DATAB
address[8] => qtriangle~0.DATAA
address[9] => LessThan~0.IN11
qtriangle[0] <= qtriangle[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qtriangle[1] <= qtriangle[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qtriangle[2] <= qtriangle[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qtriangle[3] <= qtriangle[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qtriangle[4] <= qtriangle[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qtriangle[5] <= qtriangle[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qtriangle[6] <= qtriangle[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qtriangle[7] <= qtriangle[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DDSFPGA|romlookup:inst4
address[0] => address[0]~9.IN1
address[1] => address[1]~8.IN1
address[2] => address[2]~7.IN1
address[3] => address[3]~6.IN1
address[4] => address[4]~5.IN1
address[5] => address[5]~4.IN1
address[6] => address[6]~3.IN1
address[7] => address[7]~2.IN1
address[8] => address[8]~1.IN1
address[9] => address[9]~0.IN1
clock => clock~0.IN1
clken => clken~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|DDSFPGA|romlookup:inst4|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_88s:auto_generated.address_a[0]
address_a[1] => altsyncram_88s:auto_generated.address_a[1]
address_a[2] => altsyncram_88s:auto_generated.address_a[2]
address_a[3] => altsyncram_88s:auto_generated.address_a[3]
address_a[4] => altsyncram_88s:auto_generated.address_a[4]
address_a[5] => altsyncram_88s:auto_generated.address_a[5]
address_a[6] => altsyncram_88s:auto_generated.address_a[6]
address_a[7] => altsyncram_88s:auto_generated.address_a[7]
address_a[8] => altsyncram_88s:auto_generated.address_a[8]
address_a[9] => altsyncram_88s:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_88s:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => altsyncram_88s:auto_generated.clocken0
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_88s:auto_generated.q_a[0]
q_a[1] <= altsyncram_88s:auto_generated.q_a[1]
q_a[2] <= altsyncram_88s:auto_generated.q_a[2]
q_a[3] <= altsyncram_88s:auto_generated.q_a[3]
q_a[4] <= altsyncram_88s:auto_generated.q_a[4]
q_a[5] <= altsyncram_88s:auto_generated.q_a[5]
q_a[6] <= altsyncram_88s:auto_generated.q_a[6]
q_a[7] <= altsyncram_88s:auto_generated.q_a[7]
q_b[0] <= <GND>


|DDSFPGA|romlookup:inst4|altsyncram:altsyncram_component|altsyncram_88s:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clocken0 => ram_block1a0.ENA0
clocken0 => ram_block1a1.ENA0
clocken0 => ram_block1a2.ENA0
clocken0 => ram_block1a3.ENA0
clocken0 => ram_block1a4.ENA0
clocken0 => ram_block1a5.ENA0
clocken0 => ram_block1a6.ENA0
clocken0 => ram_block1a7.ENA0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT