ddsfpga.fit.qmsg

dds设计

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DLedout\[7\] VCC " "Info: Pin DLedout\[7\] has VCC driving its datain port" {  } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 520 1720 1896 536 "DLedout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DLedout\[7\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { DLedout[7] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { DLedout[7] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 03 20:28:35 2006 " "Info: Processing ended: Wed May 03 20:28:35 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}