ddsfpga.fit.qmsg

dds设计

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.664 ns register register " "Info: Estimated most critical path is register to register delay of 7.664 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns control:inst1\|length\[9\] 1 REG LAB_X10_Y8 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y8; Fanout = 17; REG Node = 'control:inst1\|length\[9\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { control:inst1|length[9] } "NODE_NAME" } "" } } { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.519 ns) + CELL(0.575 ns) 2.094 ns control:inst1\|add~3301COUT1_3543 2 COMB LAB_X12_Y7 2 " "Info: 2: + IC(1.519 ns) + CELL(0.575 ns) = 2.094 ns; Loc. = LAB_X12_Y7; Fanout = 2; COMB Node = 'control:inst1\|add~3301COUT1_3543'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "2.094 ns" { control:inst1|length[9] control:inst1|add~3301COUT1_3543 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.174 ns control:inst1\|add~3281COUT1_3544 3 COMB LAB_X12_Y7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 2.174 ns; Loc. = LAB_X12_Y7; Fanout = 2; COMB Node = 'control:inst1\|add~3281COUT1_3544'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.080 ns" { control:inst1|add~3301COUT1_3543 control:inst1|add~3281COUT1_3544 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.254 ns control:inst1\|add~3261COUT1_3545 4 COMB LAB_X12_Y7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 2.254 ns; Loc. = LAB_X12_Y7; Fanout = 2; COMB Node = 'control:inst1\|add~3261COUT1_3545'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.080 ns" { control:inst1|add~3281COUT1_3544 control:inst1|add~3261COUT1_3545 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.334 ns control:inst1\|add~3241COUT1_3546 5 COMB LAB_X12_Y7 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 2.334 ns; Loc. = LAB_X12_Y7; Fanout = 2; COMB Node = 'control:inst1\|add~3241COUT1_3546'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.080 ns" { control:inst1|add~3261COUT1_3545 control:inst1|add~3241COUT1_3546 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.592 ns control:inst1\|add~3221 6 COMB LAB_X12_Y7 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 2.592 ns; Loc. = LAB_X12_Y7; Fanout = 6; COMB Node = 'control:inst1\|add~3221'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.258 ns" { control:inst1|add~3241COUT1_3546 control:inst1|add~3221 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.728 ns control:inst1\|add~3121 7 COMB LAB_X12_Y7 6 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 2.728 ns; Loc. = LAB_X12_Y7; Fanout = 6; COMB Node = 'control:inst1\|add~3121'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.136 ns" { control:inst1|add~3221 control:inst1|add~3121 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 3.407 ns control:inst1\|add~2939 8 COMB LAB_X12_Y6 1 " "Info: 8: + IC(0.000 ns) + CELL(0.679 ns) = 3.407 ns; Loc. = LAB_X12_Y6; Fanout = 1; COMB Node = 'control:inst1\|add~2939'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.679 ns" { control:inst1|add~3121 control:inst1|add~2939 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.321 ns) + CELL(0.114 ns) 4.842 ns control:inst1\|Select~1667 9 COMB LAB_X11_Y8 1 " "Info: 9: + IC(1.321 ns) + CELL(0.114 ns) = 4.842 ns; Loc. = LAB_X11_Y8; Fanout = 1; COMB Node = 'control:inst1\|Select~1667'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "1.435 ns" { control:inst1|add~2939 control:inst1|Select~1667 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.085 ns) + CELL(0.292 ns) 6.219 ns control:inst1\|Select~1668 10 COMB LAB_X11_Y7 1 " "Info: 10: + IC(1.085 ns) + CELL(0.292 ns) = 6.219 ns; Loc. = LAB_X11_Y7; Fanout = 1; COMB Node = 'control:inst1\|Select~1668'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "1.377 ns" { control:inst1|Select~1667 control:inst1|Select~1668 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.330 ns) + CELL(0.115 ns) 7.664 ns control:inst1\|length\[20\] 11 REG LAB_X10_Y6 18 " "Info: 11: + IC(1.330 ns) + CELL(0.115 ns) = 7.664 ns; Loc. = LAB_X10_Y6; Fanout = 18; REG Node = 'control:inst1\|length\[20\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "1.445 ns" { control:inst1|Select~1668 control:inst1|length[20] } "NODE_NAME" } "" } } { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.409 ns 31.43 % " "Info: Total cell delay = 2.409 ns ( 31.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.255 ns 68.57 % " "Info: Total interconnect delay = 5.255 ns ( 68.57 % )" {  } {  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "7.664 ns" { control:inst1|length[9] control:inst1|add~3301COUT1_3543 control:inst1|add~3281COUT1_3544 control:inst1|add~3261COUT1_3545 control:inst1|add~3241COUT1_3546 control:inst1|add~3221 control:inst1|add~3121 control:inst1|add~2939 control:inst1|Select~1667 control:inst1|Select~1668 control:inst1|length[20] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 7 " "Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 7%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}