📄 ddsfpga.fit.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 03 20:28:27 2006 " "Info: Processing started: Wed May 03 20:28:27 2006" { } { } 0} } { } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DDSFPGA -c DDSFPGA " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DDSFPGA -c DDSFPGA" { } { } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "DDSFPGA EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design \"DDSFPGA\"" { } { } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" { } { } 2} } { } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "57 57 " "Info: No exact pin location assignment(s) for 57 pins of 57 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[7\] " "Info: Pin dataout\[7\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 664 1960 2136 680 "dataout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dataout\[7\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { dataout[7] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { dataout[7] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[6\] " "Info: Pin dataout\[6\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 664 1960 2136 680 "dataout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dataout\[6\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { dataout[6] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { dataout[6] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[5\] " "Info: Pin dataout\[5\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 664 1960 2136 680 "dataout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dataout\[5\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { dataout[5] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { dataout[5] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[4\] " "Info: Pin dataout\[4\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 664 1960 2136 680 "dataout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dataout\[4\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { dataout[4] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { dataout[4] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[3\] " "Info: Pin dataout\[3\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 664 1960 2136 680 "dataout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dataout\[3\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { dataout[3] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { dataout[3] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[2\] " "Info: Pin dataout\[2\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 664 1960 2136 680 "dataout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dataout\[2\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { dataout[2] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { dataout[2] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[1\] " "Info: Pin dataout\[1\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 664 1960 2136 680 "dataout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dataout\[1\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { dataout[1] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { dataout[1] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[0\] " "Info: Pin dataout\[0\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 664 1960 2136 680 "dataout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dataout\[0\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { dataout[0] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { dataout[0] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DLedout\[7\] " "Info: Pin DLedout\[7\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 520 1720 1896 536 "DLedout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DLedout\[7\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { DLedout[7] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { DLedout[7] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DLedout\[6\] " "Info: Pin DLedout\[6\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 520 1720 1896 536 "DLedout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DLedout\[6\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { DLedout[6] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { DLedout[6] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DLedout\[5\] " "Info: Pin DLedout\[5\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 520 1720 1896 536 "DLedout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DLedout\[5\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { DLedout[5] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { DLedout[5] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DLedout\[4\] " "Info: Pin DLedout\[4\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 520 1720 1896 536 "DLedout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DLedout\[4\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { DLedout[4] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { DLedout[4] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DLedout\[3\] " "Info: Pin DLedout\[3\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 520 1720 1896 536 "DLedout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DLedout\[3\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { DLedout[3] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { DLedout[3] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DLedout\[2\] " "Info: Pin DLedout\[2\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 520 1720 1896 536 "DLedout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DLedout\[2\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { DLedout[2] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { DLedout[2] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DLedout\[1\] " "Info: Pin DLedout\[1\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 520 1720 1896 536 "DLedout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DLedout\[1\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { DLedout[1] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { DLedout[1] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DLedout\[0\] " "Info: Pin DLedout\[0\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 520 1720 1896 536 "DLedout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DLedout\[0\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { DLedout[0] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { DLedout[0] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "keyout\[7\] " "Info: Pin keyout\[7\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 832 1152 1328 848 "keyout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "keyout\[7\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { keyout[7] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { keyout[7] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "keyout\[6\] " "Info: Pin keyout\[6\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 832 1152 1328 848 "keyout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "keyout\[6\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { keyout[6] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { keyout[6] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "keyout\[5\] " "Info: Pin keyout\[5\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 832 1152 1328 848 "keyout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "keyout\[5\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { keyout[5] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { keyout[5] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "keyout\[4\] " "Info: Pin keyout\[4\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 832 1152 1328 848 "keyout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "keyout\[4\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { keyout[4] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { keyout[4] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "keyout\[3\] " "Info: Pin keyout\[3\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 832 1152 1328 848 "keyout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "keyout\[3\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { keyout[3] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { keyout[3] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "keyout\[2\] " "Info: Pin keyout\[2\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 832 1152 1328 848 "keyout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "keyout\[2\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { keyout[2] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { keyout[2] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "keyout\[1\] " "Info: Pin keyout\[1\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 832 1152 1328 848 "keyout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "keyout\[1\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { keyout[1] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { keyout[1] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "keyout\[0\] " "Info: Pin keyout\[0\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 832 1152 1328 848 "keyout\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "keyout\[0\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { keyout[0] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { keyout[0] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q\[7\] " "Info: Pin q\[7\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 896 1792 1968 912 "q\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q\[7\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { q[7] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { q[7] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q\[6\] " "Info: Pin q\[6\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 896 1792 1968 912 "q\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q\[6\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { q[6] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { q[6] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q\[5\] " "Info: Pin q\[5\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 896 1792 1968 912 "q\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q\[5\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { q[5] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { q[5] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q\[4\] " "Info: Pin q\[4\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 896 1792 1968 912 "q\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q\[4\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { q[4] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { q[4] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q\[3\] " "Info: Pin q\[3\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 896 1792 1968 912 "q\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q\[3\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { q[3] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { q[3] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q\[2\] " "Info: Pin q\[2\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 896 1792 1968 912 "q\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q\[2\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { q[2] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { q[2] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q\[1\] " "Info: Pin q\[1\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 896 1792 1968 912 "q\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q\[1\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { q[1] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { q[1] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q\[0\] " "Info: Pin q\[0\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 896 1792 1968 912 "q\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q\[0\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { q[0] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { q[0] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qsquare\[7\] " "Info: Pin qsquare\[7\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 1784 1960 640 "qsquare\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qsquare\[7\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qsquare[7] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qsquare[7] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qsquare\[6\] " "Info: Pin qsquare\[6\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 1784 1960 640 "qsquare\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qsquare\[6\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qsquare[6] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qsquare[6] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qsquare\[5\] " "Info: Pin qsquare\[5\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 1784 1960 640 "qsquare\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qsquare\[5\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qsquare[5] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qsquare[5] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qsquare\[4\] " "Info: Pin qsquare\[4\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 1784 1960 640 "qsquare\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qsquare\[4\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qsquare[4] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qsquare[4] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qsquare\[3\] " "Info: Pin qsquare\[3\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 1784 1960 640 "qsquare\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qsquare\[3\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qsquare[3] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qsquare[3] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qsquare\[2\] " "Info: Pin qsquare\[2\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 1784 1960 640 "qsquare\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qsquare\[2\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qsquare[2] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qsquare[2] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qsquare\[1\] " "Info: Pin qsquare\[1\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 1784 1960 640 "qsquare\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qsquare\[1\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qsquare[1] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qsquare[1] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qsquare\[0\] " "Info: Pin qsquare\[0\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 1784 1960 640 "qsquare\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qsquare\[0\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qsquare[0] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qsquare[0] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qtriangle\[7\] " "Info: Pin qtriangle\[7\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 856 1792 1968 872 "qtriangle\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qtriangle\[7\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qtriangle[7] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qtriangle[7] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qtriangle\[6\] " "Info: Pin qtriangle\[6\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 856 1792 1968 872 "qtriangle\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qtriangle\[6\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qtriangle[6] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qtriangle[6] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qtriangle\[5\] " "Info: Pin qtriangle\[5\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 856 1792 1968 872 "qtriangle\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qtriangle\[5\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qtriangle[5] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qtriangle[5] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qtriangle\[4\] " "Info: Pin qtriangle\[4\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 856 1792 1968 872 "qtriangle\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qtriangle\[4\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qtriangle[4] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qtriangle[4] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qtriangle\[3\] " "Info: Pin qtriangle\[3\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 856 1792 1968 872 "qtriangle\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qtriangle\[3\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qtriangle[3] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qtriangle[3] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qtriangle\[2\] " "Info: Pin qtriangle\[2\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 856 1792 1968 872 "qtriangle\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qtriangle\[2\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qtriangle[2] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qtriangle[2] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qtriangle\[1\] " "Info: Pin qtriangle\[1\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 856 1792 1968 872 "qtriangle\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qtriangle\[1\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qtriangle[1] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qtriangle[1] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qtriangle\[0\] " "Info: Pin qtriangle\[0\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 856 1792 1968 872 "qtriangle\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "qtriangle\[0\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { qtriangle[0] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { qtriangle[0] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "KeyIn\[7\] " "Info: Pin KeyIn\[7\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 744 672 840 760 "KeyIn\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "KeyIn\[7\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { KeyIn[7] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { KeyIn[7] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "KeyIn\[0\] " "Info: Pin KeyIn\[0\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 744 672 840 760 "KeyIn\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "KeyIn\[0\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { KeyIn[0] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { KeyIn[0] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "KeyIn\[2\] " "Info: Pin KeyIn\[2\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 744 672 840 760 "KeyIn\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "KeyIn\[2\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { KeyIn[2] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { KeyIn[2] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "KeyIn\[3\] " "Info: Pin KeyIn\[3\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 744 672 840 760 "KeyIn\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "KeyIn\[3\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { KeyIn[3] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { KeyIn[3] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "KeyIn\[5\] " "Info: Pin KeyIn\[5\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 744 672 840 760 "KeyIn\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "KeyIn\[5\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { KeyIn[5] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { KeyIn[5] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "KeyIn\[1\] " "Info: Pin KeyIn\[1\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 744 672 840 760 "KeyIn\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "KeyIn\[1\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { KeyIn[1] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { KeyIn[1] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "KeyIn\[6\] " "Info: Pin KeyIn\[6\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 744 672 840 760 "KeyIn\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "KeyIn\[6\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { KeyIn[6] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { KeyIn[6] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "KeyIn\[4\] " "Info: Pin KeyIn\[4\] not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 744 672 840 760 "KeyIn\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "KeyIn\[4\]" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { KeyIn[4] } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { KeyIn[4] } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" { } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 640 808 640 "clk" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { clk } "NODE_NAME" } "" } } { "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" { Floorplan "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.fld" "" "" { clk } "NODE_NAME" } } } 0} } { } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" { } { } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" { } { } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" { } { } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" { } { } 0} } { } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" { } { } 0}
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