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📄 ddsfpga.tan.qmsg

📁 dds设计
💻 QMSG
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{ "Info" "ITDB_TSU_RESULT" "Key:inst3\|scan\[13\] KeyIn\[0\] clk 4.081 ns register " "Info: tsu for register \"Key:inst3\|scan\[13\]\" (data pin = \"KeyIn\[0\]\", clock pin = \"clk\") is 4.081 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.130 ns + Longest pin register " "Info: + Longest pin to register delay is 12.130 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns KeyIn\[0\] 1 PIN PIN_26 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_26; Fanout = 2; PIN Node = 'KeyIn\[0\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { KeyIn[0] } "NODE_NAME" } "" } } { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 744 672 840 760 "KeyIn\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.734 ns) + CELL(0.114 ns) 7.317 ns Key:inst3\|reduce_nor~50 2 COMB LC_X8_Y4_N2 1 " "Info: 2: + IC(5.734 ns) + CELL(0.114 ns) = 7.317 ns; Loc. = LC_X8_Y4_N2; Fanout = 1; COMB Node = 'Key:inst3\|reduce_nor~50'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "5.848 ns" { KeyIn[0] Key:inst3|reduce_nor~50 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.292 ns) 8.047 ns Key:inst3\|reduce_nor~2 3 COMB LC_X8_Y4_N6 56 " "Info: 3: + IC(0.438 ns) + CELL(0.292 ns) = 8.047 ns; Loc. = LC_X8_Y4_N6; Fanout = 56; COMB Node = 'Key:inst3\|reduce_nor~2'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.730 ns" { Key:inst3|reduce_nor~50 Key:inst3|reduce_nor~2 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.258 ns) + CELL(0.292 ns) 9.597 ns Key:inst3\|add~348 4 COMB LC_X10_Y4_N4 3 " "Info: 4: + IC(1.258 ns) + CELL(0.292 ns) = 9.597 ns; Loc. = LC_X10_Y4_N4; Fanout = 3; COMB Node = 'Key:inst3\|add~348'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "1.550 ns" { Key:inst3|reduce_nor~2 Key:inst3|add~348 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.671 ns) + CELL(0.423 ns) 10.691 ns Key:inst3\|scan\[0\]~528 5 COMB LC_X9_Y4_N2 2 " "Info: 5: + IC(0.671 ns) + CELL(0.423 ns) = 10.691 ns; Loc. = LC_X9_Y4_N2; Fanout = 2; COMB Node = 'Key:inst3\|scan\[0\]~528'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "1.094 ns" { Key:inst3|add~348 Key:inst3|scan[0]~528 } "NODE_NAME" } "" } } { "key.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/key.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 10.769 ns Key:inst3\|scan\[1\]~520 6 COMB LC_X9_Y4_N3 2 " "Info: 6: + IC(0.000 ns) + CELL(0.078 ns) = 10.769 ns; Loc. = LC_X9_Y4_N3; Fanout = 2; COMB Node = 'Key:inst3\|scan\[1\]~520'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.078 ns" { Key:inst3|scan[0]~528 Key:inst3|scan[1]~520 } "NODE_NAME" } "" } } { "key.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/key.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 10.947 ns Key:inst3\|scan\[2\]~532 7 COMB LC_X9_Y4_N4 6 " "Info: 7: + IC(0.000 ns) + CELL(0.178 ns) = 10.947 ns; Loc. = LC_X9_Y4_N4; Fanout = 6; COMB Node = 'Key:inst3\|scan\[2\]~532'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.178 ns" { Key:inst3|scan[1]~520 Key:inst3|scan[2]~532 } "NODE_NAME" } "" } } { "key.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/key.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 11.155 ns Key:inst3\|scan\[7\]~548 8 COMB LC_X9_Y4_N9 6 " "Info: 8: + IC(0.000 ns) + CELL(0.208 ns) = 11.155 ns; Loc. = LC_X9_Y4_N9; Fanout = 6; COMB Node = 'Key:inst3\|scan\[7\]~548'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.208 ns" { Key:inst3|scan[2]~532 Key:inst3|scan[7]~548 } "NODE_NAME" } "" } } { "key.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/key.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 11.291 ns Key:inst3\|scan\[12\]~568 9 COMB LC_X9_Y3_N4 4 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 11.291 ns; Loc. = LC_X9_Y3_N4; Fanout = 4; COMB Node = 'Key:inst3\|scan\[12\]~568'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.136 ns" { Key:inst3|scan[7]~548 Key:inst3|scan[12]~568 } "NODE_NAME" } "" } } { "key.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/key.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 12.130 ns Key:inst3\|scan\[13\] 10 REG LC_X9_Y3_N5 4 " "Info: 10: + IC(0.000 ns) + CELL(0.839 ns) = 12.130 ns; Loc. = LC_X9_Y3_N5; Fanout = 4; REG Node = 'Key:inst3\|scan\[13\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.839 ns" { Key:inst3|scan[12]~568 Key:inst3|scan[13] } "NODE_NAME" } "" } } { "key.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/key.v" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.029 ns 33.22 % " "Info: Total cell delay = 4.029 ns ( 33.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.101 ns 66.78 % " "Info: Total interconnect delay = 8.101 ns ( 66.78 % )" {  } {  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "12.130 ns" { KeyIn[0] Key:inst3|reduce_nor~50 Key:inst3|reduce_nor~2 Key:inst3|add~348 Key:inst3|scan[0]~528 Key:inst3|scan[1]~520 Key:inst3|scan[2]~532 Key:inst3|scan[7]~548 Key:inst3|scan[12]~568 Key:inst3|scan[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.130 ns" { KeyIn[0] KeyIn[0]~out0 Key:inst3|reduce_nor~50 Key:inst3|reduce_nor~2 Key:inst3|add~348 Key:inst3|scan[0]~528 Key:inst3|scan[1]~520 Key:inst3|scan[2]~532 Key:inst3|scan[7]~548 Key:inst3|scan[12]~568 Key:inst3|scan[13] } { 0.000ns 0.000ns 5.734ns 0.438ns 1.258ns 0.671ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.114ns 0.292ns 0.292ns 0.423ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "key.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/key.v" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.086 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.086 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { clk } "NODE_NAME" } "" } } { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 640 808 640 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.935 ns) 3.409 ns clock_d2:inst\|clk2 2 REG LC_X8_Y7_N2 155 " "Info: 2: + IC(1.005 ns) + CELL(0.935 ns) = 3.409 ns; Loc. = LC_X8_Y7_N2; Fanout = 155; REG Node = 'clock_d2:inst\|clk2'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "1.940 ns" { clk clock_d2:inst|clk2 } "NODE_NAME" } "" } } { "clock_d2.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/clock_d2.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.966 ns) + CELL(0.711 ns) 8.086 ns Key:inst3\|scan\[13\] 3 REG LC_X9_Y3_N5 4 " "Info: 3: + IC(3.966 ns) + CELL(0.711 ns) = 8.086 ns; Loc. = LC_X9_Y3_N5; Fanout = 4; REG Node = 'Key:inst3\|scan\[13\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "4.677 ns" { clock_d2:inst|clk2 Key:inst3|scan[13] } "NODE_NAME" } "" } } { "key.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/key.v" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 38.52 % " "Info: Total cell delay = 3.115 ns ( 38.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.971 ns 61.48 % " "Info: Total interconnect delay = 4.971 ns ( 61.48 % )" {  } {  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.086 ns" { clk clock_d2:inst|clk2 Key:inst3|scan[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.086 ns" { clk clk~out0 clock_d2:inst|clk2 Key:inst3|scan[13] } { 0.000ns 0.000ns 1.005ns 3.966ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "12.130 ns" { KeyIn[0] Key:inst3|reduce_nor~50 Key:inst3|reduce_nor~2 Key:inst3|add~348 Key:inst3|scan[0]~528 Key:inst3|scan[1]~520 Key:inst3|scan[2]~532 Key:inst3|scan[7]~548 Key:inst3|scan[12]~568 Key:inst3|scan[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.130 ns" { KeyIn[0] KeyIn[0]~out0 Key:inst3|reduce_nor~50 Key:inst3|reduce_nor~2 Key:inst3|add~348 Key:inst3|scan[0]~528 Key:inst3|scan[1]~520 Key:inst3|scan[2]~532 Key:inst3|scan[7]~548 Key:inst3|scan[12]~568 Key:inst3|scan[13] } { 0.000ns 0.000ns 5.734ns 0.438ns 1.258ns 0.671ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.114ns 0.292ns 0.292ns 0.423ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.086 ns" { clk clock_d2:inst|clk2 Key:inst3|scan[13] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.086 ns" { clk clk~out0 clock_d2:inst|clk2 Key:inst3|scan[13] } { 0.000ns 0.000ns 1.005ns 3.966ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk qsquare\[1\] squwave:inst5\|qsquare\[6\] 13.980 ns register " "Info: tco from clock \"clk\" to destination pin \"qsquare\[1\]\" through register \"squwave:inst5\|qsquare\[6\]\" is 13.980 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.086 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.086 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { clk } "NODE_NAME" } "" } } { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 640 808 640 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.935 ns) 3.409 ns clock_d2:inst\|clk2 2 REG LC_X8_Y7_N2 155 " "Info: 2: + IC(1.005 ns) + CELL(0.935 ns) = 3.409 ns; Loc. = LC_X8_Y7_N2; Fanout = 155; REG Node = 'clock_d2:inst\|clk2'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "1.940 ns" { clk clock_d2:inst|clk2 } "NODE_NAME" } "" } } { "clock_d2.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/clock_d2.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.966 ns) + CELL(0.711 ns) 8.086 ns squwave:inst5\|qsquare\[6\] 3 REG LC_X12_Y2_N2 9 " "Info: 3: + IC(3.966 ns) + CELL(0.711 ns) = 8.086 ns; Loc. = LC_X12_Y2_N2; Fanout = 9; REG Node = 'squwave:inst5\|qsquare\[6\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "4.677 ns" { clock_d2:inst|clk2 squwave:inst5|qsquare[6] } "NODE_NAME" } "" } } { "squwave.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/squwave.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 38.52 % " "Info: Total cell delay = 3.115 ns ( 38.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.971 ns 61.48 % " "Info: Total interconnect delay = 4.971 ns ( 61.48 % )" {  } {  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.086 ns" { clk clock_d2:inst|clk2 squwave:inst5|qsquare[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.086 ns" { clk clk~out0 clock_d2:inst|clk2 squwave:inst5|qsquare[6] } { 0.000ns 0.000ns 1.005ns 3.966ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "squwave.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/squwave.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.670 ns + Longest register pin " "Info: + Longest register to pin delay is 5.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns squwave:inst5\|qsquare\[6\] 1 REG LC_X12_Y2_N2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y2_N2; Fanout = 9; REG Node = 'squwave:inst5\|qsquare\[6\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { squwave:inst5|qsquare[6] } "NODE_NAME" } "" } } { "squwave.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/squwave.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.546 ns) + CELL(2.124 ns) 5.670 ns qsquare\[1\] 2 PIN PIN_85 0 " "Info: 2: + IC(3.546 ns) + CELL(2.124 ns) = 5.670 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'qsquare\[1\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "5.670 ns" { squwave:inst5|qsquare[6] qsquare[1] } "NODE_NAME" } "" } } { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 1784 1960 640 "qsquare\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 37.46 % " "Info: Total cell delay = 2.124 ns ( 37.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.546 ns 62.54 % " "Info: Total interconnect delay = 3.546 ns ( 62.54 % )" {  } {  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "5.670 ns" { squwave:inst5|qsquare[6] qsquare[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.670 ns" { squwave:inst5|qsquare[6] qsquare[1] } { 0.000ns 3.546ns } { 0.000ns 2.124ns } } }  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.086 ns" { clk clock_d2:inst|clk2 squwave:inst5|qsquare[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.086 ns" { clk clk~out0 clock_d2:inst|clk2 squwave:inst5|qsquare[6] } { 0.000ns 0.000ns 1.005ns 3.966ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "5.670 ns" { squwave:inst5|qsquare[6] qsquare[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.670 ns" { squwave:inst5|qsquare[6] qsquare[1] } { 0.000ns 3.546ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "Key:inst3\|nkeyout\[4\] KeyIn\[4\] clk 5.015 ns register " "Info: th for register \"Key:inst3\|nkeyout\[4\]\" (data pin = \"KeyIn\[4\]\", clock pin = \"clk\") is 5.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.086 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.086 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { clk } "NODE_NAME" } "" } } { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 640 808 640 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.935 ns) 3.409 ns clock_d2:inst\|clk2 2 REG LC_X8_Y7_N2 155 " "Info: 2: + IC(1.005 ns) + CELL(0.935 ns) = 3.409 ns; Loc. = LC_X8_Y7_N2; Fanout = 155; REG Node = 'clock_d2:inst\|clk2'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "1.940 ns" { clk clock_d2:inst|clk2 } "NODE_NAME" } "" } } { "clock_d2.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/clock_d2.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.966 ns) + CELL(0.711 ns) 8.086 ns Key:inst3\|nkeyout\[4\] 3 REG LC_X8_Y4_N4 1 " "Info: 3: + IC(3.966 ns) + CELL(0.711 ns) = 8.086 ns; Loc. = LC_X8_Y4_N4; Fanout = 1; REG Node = 'Key:inst3\|nkeyout\[4\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "4.677 ns" { clock_d2:inst|clk2 Key:inst3|nkeyout[4] } "NODE_NAME" } "" } } { "key.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/key.v" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 38.52 % " "Info: Total cell delay = 3.115 ns ( 38.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.971 ns 61.48 % " "Info: Total interconnect delay = 4.971 ns ( 61.48 % )" {  } {  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.086 ns" { clk clock_d2:inst|clk2 Key:inst3|nkeyout[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.086 ns" { clk clk~out0 clock_d2:inst|clk2 Key:inst3|nkeyout[4] } { 0.000ns 0.000ns 1.005ns 3.966ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "key.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/key.v" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.086 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.086 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns KeyIn\[4\] 1 PIN PIN_16 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 2; PIN Node = 'KeyIn\[4\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { KeyIn[4] } "NODE_NAME" } "" } } { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 744 672 840 760 "KeyIn\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.010 ns) + CELL(0.607 ns) 3.086 ns Key:inst3\|nkeyout\[4\] 2 REG LC_X8_Y4_N4 1 " "Info: 2: + IC(1.010 ns) + CELL(0.607 ns) = 3.086 ns; Loc. = LC_X8_Y4_N4; Fanout = 1; REG Node = 'Key:inst3\|nkeyout\[4\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "1.617 ns" { KeyIn[4] Key:inst3|nkeyout[4] } "NODE_NAME" } "" } } { "key.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/key.v" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.076 ns 67.27 % " "Info: Total cell delay = 2.076 ns ( 67.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns 32.73 % " "Info: Total interconnect delay = 1.010 ns ( 32.73 % )" {  } {  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "3.086 ns" { KeyIn[4] Key:inst3|nkeyout[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.086 ns" { KeyIn[4] KeyIn[4]~out0 Key:inst3|nkeyout[4] } { 0.000ns 0.000ns 1.010ns } { 0.000ns 1.469ns 0.607ns } } }  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.086 ns" { clk clock_d2:inst|clk2 Key:inst3|nkeyout[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.086 ns" { clk clk~out0 clock_d2:inst|clk2 Key:inst3|nkeyout[4] } { 0.000ns 0.000ns 1.005ns 3.966ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "3.086 ns" { KeyIn[4] Key:inst3|nkeyout[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.086 ns" { KeyIn[4] KeyIn[4]~out0 Key:inst3|nkeyout[4] } { 0.000ns 0.000ns 1.010ns } { 0.000ns 1.469ns 0.607ns } } }  } 0}
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