ddsfpga.tan.qmsg

dds设计

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 640 808 640 "clk" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clock_d2:inst\|clk2 " "Info: Detected ripple clock \"clock_d2:inst\|clk2\" as buffer" {  } { { "clock_d2.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/clock_d2.v" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clock_d2:inst\|clk2" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register control:inst1\|length\[5\] register control:inst1\|length\[24\] 115.53 MHz 8.656 ns Internal " "Info: Clock \"clk\" has Internal fmax of 115.53 MHz between source register \"control:inst1\|length\[5\]\" and destination register \"control:inst1\|length\[24\]\" (period= 8.656 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.395 ns + Longest register register " "Info: + Longest register to register delay is 8.395 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns control:inst1\|length\[5\] 1 REG LC_X10_Y8_N5 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y8_N5; Fanout = 18; REG Node = 'control:inst1\|length\[5\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { control:inst1|length[5] } "NODE_NAME" } "" } } { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.714 ns) + CELL(0.575 ns) 2.289 ns control:inst1\|add~3371COUT1_3494 2 COMB LC_X11_Y11_N6 2 " "Info: 2: + IC(1.714 ns) + CELL(0.575 ns) = 2.289 ns; Loc. = LC_X11_Y11_N6; Fanout = 2; COMB Node = 'control:inst1\|add~3371COUT1_3494'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "2.289 ns" { control:inst1|length[5] control:inst1|add~3371COUT1_3494 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.369 ns control:inst1\|add~3351COUT1_3495 3 COMB LC_X11_Y11_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 2.369 ns; Loc. = LC_X11_Y11_N7; Fanout = 2; COMB Node = 'control:inst1\|add~3351COUT1_3495'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.080 ns" { control:inst1|add~3371COUT1_3494 control:inst1|add~3351COUT1_3495 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.449 ns control:inst1\|add~3331COUT1_3496 4 COMB LC_X11_Y11_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 2.449 ns; Loc. = LC_X11_Y11_N8; Fanout = 2; COMB Node = 'control:inst1\|add~3331COUT1_3496'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.080 ns" { control:inst1|add~3351COUT1_3495 control:inst1|add~3331COUT1_3496 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.707 ns control:inst1\|add~3311 5 COMB LC_X11_Y11_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 2.707 ns; Loc. = LC_X11_Y11_N9; Fanout = 6; COMB Node = 'control:inst1\|add~3311'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.258 ns" { control:inst1|add~3331COUT1_3496 control:inst1|add~3311 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.843 ns control:inst1\|add~3211 6 COMB LC_X11_Y10_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 2.843 ns; Loc. = LC_X11_Y10_N4; Fanout = 6; COMB Node = 'control:inst1\|add~3211'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.136 ns" { control:inst1|add~3311 control:inst1|add~3211 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 3.051 ns control:inst1\|add~3111 7 COMB LC_X11_Y10_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 3.051 ns; Loc. = LC_X11_Y10_N9; Fanout = 6; COMB Node = 'control:inst1\|add~3111'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.208 ns" { control:inst1|add~3211 control:inst1|add~3111 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 3.187 ns control:inst1\|add~2991 8 COMB LC_X11_Y9_N4 5 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 3.187 ns; Loc. = LC_X11_Y9_N4; Fanout = 5; COMB Node = 'control:inst1\|add~2991'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.136 ns" { control:inst1|add~3111 control:inst1|add~2991 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 3.808 ns control:inst1\|add~3014 9 COMB LC_X11_Y9_N5 1 " "Info: 9: + IC(0.000 ns) + CELL(0.621 ns) = 3.808 ns; Loc. = LC_X11_Y9_N5; Fanout = 1; COMB Node = 'control:inst1\|add~3014'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "0.621 ns" { control:inst1|add~2991 control:inst1|add~3014 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.699 ns) + CELL(0.442 ns) 5.949 ns control:inst1\|Select~1675 10 COMB LC_X10_Y4_N7 1 " "Info: 10: + IC(1.699 ns) + CELL(0.442 ns) = 5.949 ns; Loc. = LC_X10_Y4_N7; Fanout = 1; COMB Node = 'control:inst1\|Select~1675'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "2.141 ns" { control:inst1|add~3014 control:inst1|Select~1675 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.590 ns) 6.994 ns control:inst1\|Select~1676 11 COMB LC_X10_Y4_N8 1 " "Info: 11: + IC(0.455 ns) + CELL(0.590 ns) = 6.994 ns; Loc. = LC_X10_Y4_N8; Fanout = 1; COMB Node = 'control:inst1\|Select~1676'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "1.045 ns" { control:inst1|Select~1675 control:inst1|Select~1676 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.286 ns) + CELL(0.115 ns) 8.395 ns control:inst1\|length\[24\] 12 REG LC_X10_Y6_N4 17 " "Info: 12: + IC(1.286 ns) + CELL(0.115 ns) = 8.395 ns; Loc. = LC_X10_Y6_N4; Fanout = 17; REG Node = 'control:inst1\|length\[24\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "1.401 ns" { control:inst1|Select~1676 control:inst1|length[24] } "NODE_NAME" } "" } } { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.241 ns 38.61 % " "Info: Total cell delay = 3.241 ns ( 38.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.154 ns 61.39 % " "Info: Total interconnect delay = 5.154 ns ( 61.39 % )" {  } {  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.395 ns" { control:inst1|length[5] control:inst1|add~3371COUT1_3494 control:inst1|add~3351COUT1_3495 control:inst1|add~3331COUT1_3496 control:inst1|add~3311 control:inst1|add~3211 control:inst1|add~3111 control:inst1|add~2991 control:inst1|add~3014 control:inst1|Select~1675 control:inst1|Select~1676 control:inst1|length[24] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.395 ns" { control:inst1|length[5] control:inst1|add~3371COUT1_3494 control:inst1|add~3351COUT1_3495 control:inst1|add~3331COUT1_3496 control:inst1|add~3311 control:inst1|add~3211 control:inst1|add~3111 control:inst1|add~2991 control:inst1|add~3014 control:inst1|Select~1675 control:inst1|Select~1676 control:inst1|length[24] } { 0.000ns 1.714ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.699ns 0.455ns 1.286ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.621ns 0.442ns 0.590ns 0.115ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.096 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.096 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { clk } "NODE_NAME" } "" } } { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 640 808 640 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.935 ns) 3.409 ns clock_d2:inst\|clk2 2 REG LC_X8_Y7_N2 155 " "Info: 2: + IC(1.005 ns) + CELL(0.935 ns) = 3.409 ns; Loc. = LC_X8_Y7_N2; Fanout = 155; REG Node = 'clock_d2:inst\|clk2'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "1.940 ns" { clk clock_d2:inst|clk2 } "NODE_NAME" } "" } } { "clock_d2.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/clock_d2.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.976 ns) + CELL(0.711 ns) 8.096 ns control:inst1\|length\[24\] 3 REG LC_X10_Y6_N4 17 " "Info: 3: + IC(3.976 ns) + CELL(0.711 ns) = 8.096 ns; Loc. = LC_X10_Y6_N4; Fanout = 17; REG Node = 'control:inst1\|length\[24\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "4.687 ns" { clock_d2:inst|clk2 control:inst1|length[24] } "NODE_NAME" } "" } } { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 38.48 % " "Info: Total cell delay = 3.115 ns ( 38.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.981 ns 61.52 % " "Info: Total interconnect delay = 4.981 ns ( 61.52 % )" {  } {  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.096 ns" { clk clock_d2:inst|clk2 control:inst1|length[24] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.096 ns" { clk clk~out0 clock_d2:inst|clk2 control:inst1|length[24] } { 0.000ns 0.000ns 1.005ns 3.976ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.096 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.096 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "" { clk } "NODE_NAME" } "" } } { "DDSFPGA.bdf" "" { Schematic "E:/creat/altera/DDS/DDSFPGA/DDSFPGA.bdf" { { 624 640 808 640 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.935 ns) 3.409 ns clock_d2:inst\|clk2 2 REG LC_X8_Y7_N2 155 " "Info: 2: + IC(1.005 ns) + CELL(0.935 ns) = 3.409 ns; Loc. = LC_X8_Y7_N2; Fanout = 155; REG Node = 'clock_d2:inst\|clk2'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "1.940 ns" { clk clock_d2:inst|clk2 } "NODE_NAME" } "" } } { "clock_d2.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/clock_d2.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.976 ns) + CELL(0.711 ns) 8.096 ns control:inst1\|length\[5\] 3 REG LC_X10_Y8_N5 18 " "Info: 3: + IC(3.976 ns) + CELL(0.711 ns) = 8.096 ns; Loc. = LC_X10_Y8_N5; Fanout = 18; REG Node = 'control:inst1\|length\[5\]'" {  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "4.687 ns" { clock_d2:inst|clk2 control:inst1|length[5] } "NODE_NAME" } "" } } { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 38.48 % " "Info: Total cell delay = 3.115 ns ( 38.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.981 ns 61.52 % " "Info: Total interconnect delay = 4.981 ns ( 61.52 % )" {  } {  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.096 ns" { clk clock_d2:inst|clk2 control:inst1|length[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.096 ns" { clk clk~out0 clock_d2:inst|clk2 control:inst1|length[5] } { 0.000ns 0.000ns 1.005ns 3.976ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.096 ns" { clk clock_d2:inst|clk2 control:inst1|length[24] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.096 ns" { clk clk~out0 clock_d2:inst|clk2 control:inst1|length[24] } { 0.000ns 0.000ns 1.005ns 3.976ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.096 ns" { clk clock_d2:inst|clk2 control:inst1|length[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.096 ns" { clk clk~out0 clock_d2:inst|clk2 control:inst1|length[5] } { 0.000ns 0.000ns 1.005ns 3.976ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 23 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "control.v" "" { Text "E:/creat/altera/DDS/DDSFPGA/control.v" 23 -1 0 } }  } 0}  } { { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.395 ns" { control:inst1|length[5] control:inst1|add~3371COUT1_3494 control:inst1|add~3351COUT1_3495 control:inst1|add~3331COUT1_3496 control:inst1|add~3311 control:inst1|add~3211 control:inst1|add~3111 control:inst1|add~2991 control:inst1|add~3014 control:inst1|Select~1675 control:inst1|Select~1676 control:inst1|length[24] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.395 ns" { control:inst1|length[5] control:inst1|add~3371COUT1_3494 control:inst1|add~3351COUT1_3495 control:inst1|add~3331COUT1_3496 control:inst1|add~3311 control:inst1|add~3211 control:inst1|add~3111 control:inst1|add~2991 control:inst1|add~3014 control:inst1|Select~1675 control:inst1|Select~1676 control:inst1|length[24] } { 0.000ns 1.714ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.699ns 0.455ns 1.286ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.621ns 0.442ns 0.590ns 0.115ns } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.096 ns" { clk clock_d2:inst|clk2 control:inst1|length[24] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.096 ns" { clk clk~out0 clock_d2:inst|clk2 control:inst1|length[24] } { 0.000ns 0.000ns 1.005ns 3.976ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" "" { Report "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA_cmp.qrpt" Compiler "DDSFPGA" "UNKNOWN" "V1" "E:/creat/altera/DDS/DDSFPGA/db/DDSFPGA.quartus_db" { Floorplan "E:/creat/altera/DDS/DDSFPGA/" "" "8.096 ns" { clk clock_d2:inst|clk2 control:inst1|length[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.096 ns" { clk clk~out0 clock_d2:inst|clk2 control:inst1|length[5] } { 0.000ns 0.000ns 1.005ns 3.976ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}