squwave.v

来自「dds设计」· Verilog 代码 · 共 23 行

//squwave.v	 	产生方波模块	2006-5-1	version:1.0		作者：田世坤
module squwave(clk,enable,address,qsquare);
	input clk,enable;
	input [9:0] address;
	output [7:0] qsquare;
	reg [7:0] qsquare;
	
		
	always @ (posedge clk)
	begin
		if(!enable)
			qsquare = 8'b00000000;
		else
		begin
			if(address <= 10'b0111111111)
				qsquare[7:0] = 8'b11111111;
			else
				qsquare[7:0] = 8'b00000000;
		end	
	end	
	
endmodule