squwave.v.bak

dds设计

//squwave.v	 	产生方波模块	2006-5-1	version:1.0		作者：田世坤
module squwave(clk,enable,address,qsquare);
	input clk,enable;
	input [8:0] address;
	output [7:0] qsquare;
	reg [7:0] qsquare;
	
		
	always @ (posedge clk)
	begin
		if(!enable)
			qsquare[7:0] = 8'b0;
		else
			qsquare[7:0] = ~qsquare[7:0];
			
	end	
	
endmodule