triawave.v

来自「dds设计」· Verilog 代码 · 共 27 行

//triawave.v	 	产生三角波模块   2006-5-1	version:1.0		作者：田世坤
module triawave(clk,enable,address,qtriangle);
input clk, enable;
input [9:0] address;
output [7:0] qtriangle;
reg [7:0] qtriangle;

reg [9:0] temp;
	
	always @ (posedge clk)
	begin
		if(!enable)
			qtriangle = 8'b00000000;
		else
		begin
			if(address <= 10'b0111111111)
			begin
				qtriangle[7:0] = address[8:1];
			end	
		  	else
			begin
				temp = ~address;
				qtriangle[7:0] = temp[8:1];
			end
		end
	end
endmodule