clock_d2.v

来自「dds设计」· Verilog 代码 · 共 13 行

//name:clock_d2.v       二分频模块 	2006-5-2	version:1.0		作者：田世坤
//：
module clock_d2(clk,clk2);
input clk;
output clk2;
reg clk2;

always @ (posedge clk)
	begin
		clk2 = ~clk2;
	end

endmodule