ddsfpga.map.rpt

dds设计

; Parameter Name                     ; Value          ; Type                                   ;
+------------------------------------+----------------+----------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8              ; Untyped                                ;
; AUTO_CARRY_CHAINS                  ; ON             ; AUTO_CARRY                             ;
; IGNORE_CARRY_BUFFERS               ; OFF            ; IGNORE_CARRY                           ;
; AUTO_CASCADE_CHAINS                ; ON             ; AUTO_CASCADE                           ;
; IGNORE_CASCADE_BUFFERS             ; OFF            ; IGNORE_CASCADE                         ;
; OPERATION_MODE                     ; ROM            ; Untyped                                ;
; WIDTH_A                            ; 8              ; Integer                                ;
; WIDTHAD_A                          ; 10             ; Integer                                ;
; NUMWORDS_A                         ; 1024           ; Integer                                ;
; OUTDATA_REG_A                      ; CLOCK0         ; Untyped                                ;
; ADDRESS_ACLR_A                     ; NONE           ; Untyped                                ;
; OUTDATA_ACLR_A                     ; NONE           ; Untyped                                ;
; WRCONTROL_ACLR_A                   ; NONE           ; Untyped                                ;
; INDATA_ACLR_A                      ; NONE           ; Untyped                                ;
; BYTEENA_ACLR_A                     ; NONE           ; Untyped                                ;
; WIDTH_B                            ; 1              ; Untyped                                ;
; WIDTHAD_B                          ; 1              ; Untyped                                ;
; NUMWORDS_B                         ; 1              ; Untyped                                ;
; INDATA_REG_B                       ; CLOCK1         ; Untyped                                ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1         ; Untyped                                ;
; RDCONTROL_REG_B                    ; CLOCK1         ; Untyped                                ;
; ADDRESS_REG_B                      ; CLOCK1         ; Untyped                                ;
; OUTDATA_REG_B                      ; UNREGISTERED   ; Untyped                                ;
; BYTEENA_REG_B                      ; CLOCK1         ; Untyped                                ;
; INDATA_ACLR_B                      ; NONE           ; Untyped                                ;
; WRCONTROL_ACLR_B                   ; NONE           ; Untyped                                ;
; ADDRESS_ACLR_B                     ; NONE           ; Untyped                                ;
; OUTDATA_ACLR_B                     ; NONE           ; Untyped                                ;
; RDCONTROL_ACLR_B                   ; NONE           ; Untyped                                ;
; BYTEENA_ACLR_B                     ; NONE           ; Untyped                                ;
; WIDTH_BYTEENA_A                    ; 1              ; Integer                                ;
; WIDTH_BYTEENA_B                    ; 1              ; Untyped                                ;
; RAM_BLOCK_TYPE                     ; M4K            ; Untyped                                ;
; BYTE_SIZE                          ; 8              ; Untyped                                ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE      ; Untyped                                ;
; INIT_FILE                          ; 1024.mif       ; Untyped                                ;
; INIT_FILE_LAYOUT                   ; PORT_A         ; Untyped                                ;
; MAXIMUM_DEPTH                      ; 0              ; Untyped                                ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL         ; Untyped                                ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL         ; Untyped                                ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL         ; Untyped                                ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL         ; Untyped                                ;
; DEVICE_FAMILY                      ; Cyclone        ; Untyped                                ;
; CBXI_PARAMETER                     ; altsyncram_88s ; Untyped                                ;
+------------------------------------+----------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/creat/altera/DDS/DDSFPGA/DDSFPGA.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed May 03 20:28:19 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDSFPGA -c DDSFPGA
Info: Found 1 design units, including 1 entities, in source file romlookup.v
    Info: Found entity 1: romlookup
Info: Found 1 design units, including 1 entities, in source file DDSFPGA.bdf
    Info: Found entity 1: DDSFPGA
Info: Found 1 design units, including 1 entities, in source file key.v
    Info: Found entity 1: Key
Info: Found 1 design units, including 1 entities, in source file control.v
    Info: Found entity 1: control
Info: Found 1 design units, including 1 entities, in source file squwave.v
    Info: Found entity 1: squwave
Info: Found 1 design units, including 1 entities, in source file triawave.v
    Info: Found entity 1: triawave
Info: Found 1 design units, including 1 entities, in source file datachoose.v
    Info: Found entity 1: datachoose
Info: Found 1 design units, including 1 entities, in source file clock_d2.v
    Info: Found entity 1: clock_d2
Info: Elaborating entity "DDSFPGA" for the top level hierarchy
Info: Elaborating entity "datachoose" for hierarchy "datachoose:inst2"
Info: Verilog HDL Case Statement information at datachoose.v(13): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement
Info: Elaborating entity "clock_d2" for hierarchy "clock_d2:inst"
Info: Elaborating entity "control" for hierarchy "control:inst1"
Info: Elaborating entity "Key" for hierarchy "Key:inst3"
Info: Elaborating entity "squwave" for hierarchy "squwave:inst5"
Info: Elaborating entity "triawave" for hierarchy "triawave:inst6"
Info: Elaborating entity "romlookup" for hierarchy "romlookup:inst4"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "romlookup:inst4|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_88s.tdf
    Info: Found entity 1: altsyncram_88s
Info: Elaborating entity "altsyncram_88s" for hierarchy "romlookup:inst4|altsyncram:altsyncram_component|altsyncram_88s:auto_generated"
Info: Power-up level of register "control:inst1|DLedout[7]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "control:inst1|DLedout[7]" with stuck data_in port to stuck value VCC
Info: Duplicate registers merged to single register
    Info: Duplicate register "squwave:inst5|qsquare[7]" merged to single register "squwave:inst5|qsquare[6]"
    Info: Duplicate register "squwave:inst5|qsquare[5]" merged to single register "squwave:inst5|qsquare[6]"
    Info: Duplicate register "squwave:inst5|qsquare[4]" merged to single register "squwave:inst5|qsquare[6]"
    Info: Duplicate register "squwave:inst5|qsquare[3]" merged to single register "squwave:inst5|qsquare[6]"
    Info: Duplicate register "squwave:inst5|qsquare[2]" merged to single register "squwave:inst5|qsquare[6]"
    Info: Duplicate register "squwave:inst5|qsquare[1]" merged to single register "squwave:inst5|qsquare[6]"
    Info: Duplicate register "squwave:inst5|qsquare[0]" merged to single register "squwave:inst5|qsquare[6]"
Info: State machine "|DDSFPGA|control:inst1|state_wave" contains 3 states and 0 state bits
Info: State machine "|DDSFPGA|control:inst1|state_adjust" contains 3 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|DDSFPGA|control:inst1|state_wave"
Info: Encoding result for state machine "|DDSFPGA|control:inst1|state_wave"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "control:inst1|state_wave.sin"
        Info: Encoded state bit "control:inst1|state_wave.triangle"
        Info: Encoded state bit "control:inst1|state_wave.square"
    Info: State "|DDSFPGA|control:inst1|state_wave.square" uses code string "000"
    Info: State "|DDSFPGA|control:inst1|state_wave.triangle" uses code string "011"
    Info: State "|DDSFPGA|control:inst1|state_wave.sin" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|DDSFPGA|control:inst1|state_adjust"
Info: Encoding result for state machine "|DDSFPGA|control:inst1|state_adjust"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "control:inst1|state_adjust.adj10k"
        Info: Encoded state bit "control:inst1|state_adjust.adj100"
        Info: Encoded state bit "control:inst1|state_adjust.adj1"
    Info: State "|DDSFPGA|control:inst1|state_adjust.adj10k" uses code string "000"
    Info: State "|DDSFPGA|control:inst1|state_adjust.adj100" uses code string "110"
    Info: State "|DDSFPGA|control:inst1|state_adjust.adj1" uses code string "101"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "DLedout[7]" stuck at VCC
Info: Implemented 388 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 48 output pins
    Info: Implemented 323 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Wed May 03 20:28:25 2006
    Info: Elapsed time: 00:00:07