triawave.v.bak

dds设计

//triawave.v	 	产生三角波模块   2006-5-1	version:1.0		作者：田世坤
module triawave(clk,enable,address,qtriangle);
input clk,enable;
input [8:0] address;
output [7:0] qtriangle;
reg [7:0] qtriangle;
	
	always @ (posedge clk)
	begin
		if(qtriangle = 8'b00000000)
			qtriangle = qtriangle + 8'b01111111;
		if(qtriangle = 8'b11111110)
			qtriangle = qtriangle - 8'b01111111;
	end

endmodule