📄 dk3200ee_0.plg
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Current project is: 'dk3200ee'
WARNING :
In 'Chip Select Equations' tab under 'Design Assistant'
The following signal(s) exceed the maximum chip select size.
rs0, fs0, fs1, fs2, fs3.
WARNING :
In 'Chip Select Equations' tab under 'Design Assistant'
The following signal(s) exceed the maximum chip select size.
rs0, fs0, fs1, fs2, fs3.
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'dk3200ee'
Processing equations.........
Module parsing complete. Building logic network...
Creating Berkeley PLA file dk3200ee.tt1...
Module 'dk3200ee' processing complete.
Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds
BLIFOPT Open-ABEL Optimizer
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Reading Open-ABEL (PLA) file dk3200ee.tt1...
Performing 'bypin choose' optimization...
Shortening signal names...
Writing signal name cross reference file dk3200ee.xrf...
Writing Open-ABEL (PLA) file dk3200ee.tt2...
BLIFOPT complete - 0 errors, 0 warnings. Time: 1 seconds
DIOFFT Flip-Flop Transformation program
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Input file: dk3200ee.tt2.
Output file: dk3200ee.tt3.
DIOFFT complete. - Time 0 seconds
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'dk3200ee'
Processing equations.........
Module parsing complete. Building logic network...
Creating Berkeley PLA file dk3200ee.tt1...
Module 'dk3200ee' processing complete.
Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'dk3200ee'
Processing equations..........
Module parsing complete. Building logic network...
Creating Berkeley PLA file dk3200ee.tt1...
Module 'dk3200ee' processing complete.
Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds
BLIFOPT Open-ABEL Optimizer
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Reading Open-ABEL (PLA) file dk3200ee.tt1...
Performing 'bypin choose' optimization...
Shortening signal names...
Writing signal name cross reference file dk3200ee.xrf...
Writing Open-ABEL (PLA) file dk3200ee.tt2...
BLIFOPT complete - 0 errors, 0 warnings. Time: 2 seconds
DIOFFT Flip-Flop Transformation program
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Input file: dk3200ee.tt2.
Output file: dk3200ee.tt3.
........
DIOFFT complete. - Time 0 seconds
PSD Fitter - Logic Synthesis and Device Fitting
PSDsoft Express 8.00 Copyright (C) 1993-2003 STMicroelectronics, Inc. All Rights Reserved.
PROJECT : dk3200ee DATE : 10/13/2004
DEVICE : uPSD3212C TIME : 09:46:58
FIT OPTION : Keep Current
DESCRIPTION: Demo for uPSD3234A EEPROM emulation
>> Warning FIT379 : 'tdo' is a dedicated JTAG pin. Please ensure that
>> there is no signal contention.
>> Warning FIT379 : 'tdi' is a dedicated JTAG pin. Please ensure that
>> there is no signal contention.
>> Warning FIT379 : 'tck' is a dedicated JTAG pin. Please ensure that
>> there is no signal contention.
>> Warning FIT379 : 'tms' is a dedicated JTAG pin. Please ensure that
>> there is no signal contention.
>> Warning FIT170 : Bus control function, '_psen' is not required in the 'psel0' equation.
>> PSD Fitter complete - Successful Fitting
>> View fitter report for detail
PSD Address Translation - Merge MCU Firmware with PSD
PSDsoft Express 8.00 Copyright (C) 1993-2003 STMicroelectronics, Inc. All Rights Reserved.
PROJECT : dk3200ee DATE : 10/13/2004
DEVICE : uPSD3212C TIME : 09:47:32
>>
>> Warning ADR002: No data file has been specified for FS1.
>> Warning ADR002: No data file has been specified for FS2.
>> Warning ADR002: No data file has been specified for FS3.
>> Warning ADR002: No data file has been specified for CSBOOT0.
>> Warning ADR002: No data file has been specified for CSBOOT1.
>> Address Translation complete.
>>
PSD Address Translation - Merge MCU Firmware with PSD
PSDsoft Express 8.00 Copyright (C) 1993-2003 STMicroelectronics, Inc. All Rights Reserved.
PROJECT : dk3200ee DATE : 10/13/2004
DEVICE : uPSD3212C TIME : 09:48:36
>>
>> Warning ADR002: No data file has been specified for FS1.
>> Warning ADR002: No data file has been specified for FS2.
>> Warning ADR002: No data file has been specified for FS3.
>> Warning ADR002: No data file has been specified for CSBOOT0.
>> Warning ADR002: No data file has been specified for CSBOOT1.
>> Address Translation complete.
>>
PSD Address Translation - Merge MCU Firmware with PSD
PSDsoft Express 8.00 Copyright (C) 1993-2003 STMicroelectronics, Inc. All Rights Reserved.
PROJECT : dk3200ee DATE : 10/13/2004
DEVICE : uPSD3212C TIME : 09:49:01
>>
>> Warning ADR002: No data file has been specified for FS1.
>> Warning ADR002: No data file has been specified for FS2.
>> Warning ADR002: No data file has been specified for FS3.
>> Warning ADR002: No data file has been specified for CSBOOT0.
>> Warning ADR002: No data file has been specified for CSBOOT1.
>> Address Translation complete.
>>
WARNING :
In 'Chip Select Equations' tab under 'Design Assistant'
The following signal(s) exceed the maximum chip select size.
rs0, fs0, fs1, fs2, fs3.
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'dk3200ee'
Processing equations.........
Module parsing complete. Building logic network...
Creating Berkeley PLA file dk3200ee.tt1...
Module 'dk3200ee' processing complete.
Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 2 seconds
BLIFOPT Open-ABEL Optimizer
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Reading Open-ABEL (PLA) file dk3200ee.tt1...
Performing 'bypin choose' optimization...
Shortening signal names...
Writing signal name cross reference file dk3200ee.xrf...
Writing Open-ABEL (PLA) file dk3200ee.tt2...
BLIFOPT complete - 0 errors, 0 warnings. Time: 1 seconds
DIOFFT Flip-Flop Transformation program
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Input file: dk3200ee.tt2.
Output file: dk3200ee.tt3.
DIOFFT complete. - Time 0 seconds
WARNING :
In 'Chip Select Equations' tab under 'Design Assistant'
The following signal(s) exceed the maximum chip select size.
rs0.
WARNING :
In 'Chip Select Equations' tab under 'Design Assistant'
The following signal(s) exceed the maximum chip select size.
rs0.
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'dk3200ee'
Processing equations.........
Module parsing complete. Building logic network...
Creating Berkeley PLA file dk3200ee.tt1...
Module 'dk3200ee' processing complete.
Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds
BLIFOPT Open-ABEL Optimizer
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Reading Open-ABEL (PLA) file dk3200ee.tt1...
Performing 'bypin choose' optimization...
Shortening signal names...
Writing signal name cross reference file dk3200ee.xrf...
Writing Open-ABEL (PLA) file dk3200ee.tt2...
BLIFOPT complete - 0 errors, 0 warnings. Time: 1 seconds
DIOFFT Flip-Flop Transformation program
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Input file: dk3200ee.tt2.
Output file: dk3200ee.tt3.
DIOFFT complete. - Time 0 seconds
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'dk3200ee'
Processing equations.........
Module parsing complete. Building logic network...
Creating Berkeley PLA file dk3200ee.tt1...
Module 'dk3200ee' processing complete.
Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds
AHDL2BLF ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'dk3200ee'
Processing equations..........
Module parsing complete. Building logic network...
Creating Berkeley PLA file dk3200ee.tt1...
Module 'dk3200ee' processing complete.
Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds
BLIFOPT Open-ABEL Optimizer
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Reading Open-ABEL (PLA) file dk3200ee.tt1...
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