sram_rd_wr.vhd

The Hardware folder contains the following files:- 1) Sram_Interface.bit -----------------> Bi

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity SRAM_RD_WR is
port(	  
	rst			: in 	std_logic; -- 
	Clk			: in 	std_logic; --
	init			: in std_logic;				 
	read_writebar	: in	std_logic;
	Data_SRAM	 : inout std_logic_vector(15 downto 0); --
	addr_load	 : in std_logic ;
	Address_SRAM_in : in std_logic_vector(19 downto 0); --
	Cs_bar_sram	 : out 	std_logic; --
	Wr_bar_sram	 : out 	std_logic; --
	OE_bar_sram	 : out 	std_logic; --	 
	Data_in		 : in 	std_logic_vector(15 downto 0); --
	Data_out		 : out 	std_logic_vector(15 downto 0);--
	Address_SRAM : out 	std_logic_vector(19 downto 0);
	send_data_sram_ctrl	: in 	std_logic;	
	Data_En_out	: out 	std_logic;
--	address_pulse	: out   std_logic;
	Data_ready_in	: in 	std_logic
	);
end SRAM_RD_WR;

architecture Behavioral of SRAM_RD_WR is

type state is (start,chip_sel, rd_en1,rd_en2, data_latch, data_en );
signal 	ps, ns : state ;

type state1 is ( start, dly, wr_en1, wr_en2, cs_dis, addr_en );
signal ps1, ns1 : state1 ;

signal cs_bar_rd,rd_bar,wr_bar_en,cs_bar_wr, d_en , read_write_bar,add_en  : std_logic; 
signal Address_out_SRAM_rd : std_logic_vector(19 downto 0); 
signal Address_out_SRAM_wr : std_logic_vector(19 downto 0);
signal Data_SRAM_wr : std_logic_vector(15 downto 0);
signal Data_SRAM_rd : std_logic_vector(15 downto 0);

begin

read_write_bar <= read_writebar;

--------------------------------Multiplexer For ADDRESS SRAM --------------------------------
--	address_pulse   <= 	d_en  when read_write_bar = '1' else add_en;
	
	Address_SRAM	<=	Address_out_SRAM_rd when read_write_bar = '1' else			   -- SRAM ADDRESS              	 
							Address_out_SRAM_wr;	
	
	Cs_bar_sram	<=	cs_bar_rd when read_write_bar = '1' else	   -- Chip Select for SRAM
	                  	cs_bar_wr;


------------------------TRANSFERING DATA FROM AND TO SRAM BUS---------------------------------

 Data_SRAM <= 	Data_sram_wr when (rd_bar = '1' and cs_bar_wr = '0') else	  -- Data Bus SARM
		(others => 'Z' );

 process(Clk,rst, Data_SRAM, init,ps)
 begin
 if (rst = '1' or init = '0') then
   	Data_sram_rd <= (others => '0');
 elsif Clk'event and Clk = '0' then
  if ps = rd_en2 then
	Data_sram_rd <= Data_SRAM;
  end if;
 end if;
 end process;
----------------------- FSM GENERATING THE DATA READY SIGNAL FOR UART------------------------------------------

	OE_bar_sram 	<= rd_bar;	-- Read Enable For SRAM
	Wr_bar_sram 	<= wr_bar_en;	-- Write Enable For SRAM
	Data_out 	<= Data_sram_rd;-- 16 bit output from SRAM 
					--  is Given out for Transmitter
	
process(rst, Clk,read_write_bar, ns, init)
begin
	if (rst = '1' or read_write_bar = '0' or init = '0') then	   
	  ps <= start;
	elsif Clk'event and Clk = '1' then
	  ps <= ns ;
	end if;
end process;

process(ps,send_data_sram_ctrl)		--send_data_sram_ctrl
begin
	case ps is 
	  when start =>
	   if send_data_sram_ctrl = '1' then	--- If Transmitter is ready to Transmit then send_data_sram_ctrl should intimate the controller
		ns <= chip_sel;
	   else 
		ns <= start;
	   end if;
	  when chip_sel =>
	       ns <= rd_en1 ;	   
	  when rd_en1 =>	-- generates read enable for SRAM
	    ns <= rd_en2 ;
	  when rd_en2 =>
	    ns <= data_latch;
	  when data_latch =>
	    ns <= data_en ;
	  when data_en =>
	    ns <= start ;
	  when others =>
	    ns <= start ;
	  end case ;
 end process;



process(ps)			--send_data_sram_ctrl
begin
	case ps is 	  
	 when start =>
	  cs_bar_rd <= '1' ;
	  rd_bar <= '1' ;
	  d_en <= '0' ;
	 when chip_sel =>
--	  if send_data_sram_ctrl = '1' then
	  cs_bar_rd <= '0' ;
--	  else
--	  cs_bar_rd <= '1' ;
--	  end if;
	  rd_bar <= '1' ;
	  d_en <= '0' ;
	 when rd_en1 =>
	  cs_bar_rd <= '0' ;
	  rd_bar <= '0' ;
	  d_en <= '0' ;
	 when rd_en2 =>
	  cs_bar_rd <= '0' ;
	  rd_bar <= '0' ;
	  d_en <= '0' ;
	 when data_latch =>
	  cs_bar_rd <= '0' ;
	  rd_bar <= '1' ;
	  d_en <= '0' ;
	 when data_en =>
	  cs_bar_rd <= '1' ;
	  rd_bar <= '1' ;
	  d_en <= '1' ;	  ---  d_en indicates to the Transmitter that it can now take 16 bit data
--	 when others =>
--	  cs_bar_rd <= '1' ;
--	  rd_bar <= '1' ;
--	  d_en <= '0' ;
	  end case ;
 end process;

 Data_En_out <= d_en ;

------------------------------------------SRAM READ ADDRESS------------------------------------------------------
 process(rst, d_en, read_write_bar,Clk,Address_SRAM_in, init,addr_load) 
 begin	
 	if (rst = '1'or read_write_bar = '0' or init = '0' ) then	 
		Address_out_SRAM_rd <= (others => '0'); 
	elsif addr_load = '1' then
		Address_out_SRAM_rd <= Address_SRAM_in;
	elsif Clk'event and Clk = '0' then 
		if d_en = '1' then
			Address_out_SRAM_rd <= Address_out_SRAM_rd  + 1; 
		end if;
	end if;
end process;
------------------------------------FSM FOR GENERATING SIGNALS FOR WRITING TOSRAM-------------------------------

process(Data_ready_in,Clk,rst, Data_in, init)
begin
if ( rst ='1' or init = '0') then
	data_SRAM_wr <= (others => '0');
elsif Clk'event and Clk = '0' then
 	  if Data_ready_in = '1' then               --- When 16 bit data is received then it will be taken in on  Data_ready_in
 	   data_SRAM_wr <= Data_in;
      end if;
end if;
end process;

process(rst, Clk, read_write_bar, ns1, init)
begin
	if (rst = '1' or read_write_bar = '1' or init = '0') then	
	  ps1 <= start ;
	elsif Clk'event and Clk = '1' then
	  ps1 <= ns1 ;
	end if;
end process ;


process(ps1, Data_ready_in)
begin
	case ps1 is 	  
	  when start =>
	   if Data_ready_in = '1' then
	    ns1 <= dly;
	   else
	    ns1 <= start;
	   end if;
	  when dly =>
	    ns1 <= wr_en1;
	  when wr_en1 =>	  	 -- Generates wr enable forSRAM
	    ns1 <= wr_en2;
	  when wr_en2 =>
	    ns1 <= cs_dis;
	  when cs_dis =>
	    ns1 <= addr_en;
	  when addr_en =>
	    ns1 <= start;
	  when others =>
	    ns1 <= start;
	end case;
end process;

process(ps1, Data_ready_in)
begin
	case ps1 is 	  
	 when start =>
	  if Data_ready_in = '1' then
	  cs_bar_wr <= '0' ;
	  else
	  cs_bar_wr <= '1' ;
	  end if ;
	  add_en <= '0' ;
	  wr_bar_en <= '1';
	 when dly =>
	  cs_bar_wr <= '0' ;
	  add_en <= '0' ;
	  wr_bar_en <= '1';
	 when wr_en1 =>
	  cs_bar_wr <= '0';
	  add_en <= '0' ;
	  wr_bar_en <= '0';
	 when wr_en2 =>
	  cs_bar_wr <= '0';
	  add_en <= '0';
	  wr_bar_en <= '0';
	 when cs_dis =>
	  cs_bar_wr <= '0' ;
	  add_en <= '0' ;
	  wr_bar_en <= '1';
	 when addr_en =>
	  cs_bar_wr <= '1' ;
	  add_en <= '1' ;
	  wr_bar_en <= '1';
	 when others =>
	  cs_bar_wr <= '1' ;
	  add_en <= '0' ;
	  wr_bar_en <= '1';
	end case ;
end process ;	  


 ---------------------------------------WRITE Address  for SRAM ---------------------------------------
 process(rst,Clk, add_en,Address_SRAM_in, init, addr_load)
 begin
  if ( rst = '1' or init = '0') then 
 		Address_out_SRAM_wr <= (others => '0'); 
  elsif addr_load = '1' then
		Address_out_SRAM_wr <= Address_SRAM_in;
	elsif Clk'event and Clk = '0' then 
		if add_en = '1' then
			Address_out_SRAM_wr <= Address_out_SRAM_wr + 1 ; 
		end if;
	end if; 
end process;

--==========================================================================================================================================
end Behavioral;
--==========================================================================================================================================