sram_interface.vhd

The Hardware folder contains the following files:- 1) Sram_Interface.bit -----------------> Bi

--=====================================CHIP SELECT FOR SRAMS =============================

	Init1 <= CWR_s(3);

	Init2 <= CWR_s(4);
	Init3 <= CWR_s(5);
	Init4 <= CWR_s(6);
	Init5 <= CWR_s(7);

--=======================LATCHING THE ADDRESS FOR SRAM=====================================

process (pci_clk,reset_s,dtr, den, address, pci_bus)
begin
	if(reset_s = '1') then
	 address_in <= (others => '0');
	elsif(pci_clk'event and pci_clk = '1') then
		if(dtr = '1' and den = '0' and address(15 downto 0) = x"0004") then
			address_in <= Pci_bus;
		end if;
	end if;
end process;

	Address_SRAM_in <= Address_in(19 downto 0) ;

--=======================Generating Address_load_en for SRAM1=====================================

process(pci_clk,reset_s)
begin	
	if reset_s  = '1' then
		ps1 <= start2;
	elsif pci_clk'event and pci_clk = '1' then
		ps1 <= ns1 ;
	end if;
end process;

process(ps1, Address, den, dtr)
begin
	case ps1 is 
		when start2 => 
			if ( Address(15 downto 0) = x"0004" and den = '0' and dtr = '1' ) then
				ns1 <= dly2;
			else	
				ns1 <= start2;
			end if;

		when dly2 =>
			ns1 <= addr_en ;

		when addr_en =>
			ns1 <= start2;

		when others =>
			ns1 <= start2;
	end case;
end process;


process(ps1)
begin
	
	case ps1 is 
		when start2 => 
			  address_load <= '0';
		when dly2 =>
				address_load <= '0';
		when addr_en =>
				address_load <= '1';
	end case;
end process;

--===============================================================================================
	
	Read_Write <= CWR_S(2);		  -------------- Read_Write = '1' ======> READ
					   					  -------------- Read_Write = '0' ======> WRITE


--=======================LATCHING THE DATA FOR SRAM=====================================

process (pci_clk,reset_s,dtr, den, address, pci_bus)
begin
	if(reset_s = '1') then
	 	Data_s <= (others => '0');
	elsif(pci_clk'event and pci_clk = '1') then
		if(dtr = '1' and den = '0' and address(15 downto 0) = x"0008") then
			Data_s <= Pci_bus;
		end if;
	end if;
end process;

	data_in_sram <= data_s(15 downto 0);
	
--=======================FSM FOR GENERATING SIGNALS FOR WRITING TO SRAM================

process(pci_clk,reset_s)
begin	
	if reset_s = '1' then	
		ps <= start;
	elsif pci_clk'event and pci_clk = '1' then
		ps <= ns ;
	end if;
end process;


process(ps, den, dtr, address)
begin	
	case ps is 
		when start =>
			if (den = '0' and dtr = '1' and address(15 downto 0) = x"0008") then
				ns <= dly ;
			else
				ns <= start;
			end if ;
		when dly =>
			ns <= en_gen;
		when en_gen=>
			ns <= stop;
		when stop =>
			ns <= start;
		when others =>
			ns <= start;
	end case;
end process;
		


process(ps)
begin	
	case ps is 
		when start =>
			den_in <= '0';	
	
		when dly =>
			den_in <= '0';

		when en_gen=>
			den_in <= '1';		

		when stop =>
			den_in <= '0';	
		
	end case;
end process;

--======================================================================================


process(pci_clk,reset_s)
begin	
	if reset_s = '1' then	
		p_s <= start1;
	elsif pci_clk'event and pci_clk = '1' then
		p_s <= n_s ;
	end if;
end process;


process(p_s,CWR_s,address,den,dtr)
begin	
	case p_s is 
		when start1 =>
			if (CWR_s(2) = '1'and den = '0' and dtr = '0') then
				n_s <= en_gen1 ;
			else
				n_s <= start1;
			end if ;

		when en_gen1=>
			n_s <= stop1;

		when stop1 =>
			if (den = '0' and dtr = '0') then
				n_s <= dly1 ;
			else
				n_s <= stop1;
			end if;

		when dly1 =>
			n_s <= start1;	
		when others =>
			n_s <= start1;
	end case;
end process;


process(p_s)
begin	
	case p_s is 
		when start1 =>
			send_en_rd <= '0';
		when en_gen1=>
			send_en_rd <= '1';			
		when dly1 =>
			send_en_rd <= '0';
		when stop1 =>
			send_en_rd <= '0';
	end case;
end process;


--======================================================================================		

--process (pci_clk,reset_s,den_out1,data_out_sram_s1)
--begin
--	if(reset_s = '1') then
--		data_out_sram1 <= (others => '0');
--	elsif(pci_clk'event and pci_clk = '0') then
--		if(den_out1 = '1') then
--				data_out_sram1 <= data_out_sram_s1;
--		end if;
--	end if;
--end process;

--process (pci_clk,reset_s,den_out2,data_out_sram_s2)
--begin
--	if(reset_s = '1') then
--		data_out_sram2 <= (others => '0');
--	elsif(pci_clk'event and pci_clk = '0') then
--		if(den_out2 = '1') then
--				data_out_sram2 <= data_out_sram_s2;
--		end if;
--	end if;
--end process;


--process (pci_clk,reset_s,den_out3,data_out_sram_s3)
--begin
--	if(reset_s = '1') then
--		data_out_sram3 <= (others => '0');
--	elsif(pci_clk'event and pci_clk = '0') then
--		if(den_out3 = '1') then
--			data_out_sram3 <= data_out_sram_s3;
--		end if;
--	end if;
--end process;


--process (pci_clk,reset_s,den_out4,data_out_sram_s4)
--begin
--	if(reset_s = '1') then
--		data_out_sram2 <= (others => '0');
--	elsif(pci_clk'event and pci_clk = '0') then
--		if(den_out4 = '1') then
--			data_out_sram4 <= data_out_sram_s4;
--		end if;
--	end if;
--end process;



	Data_out_Sram <= Data_out_sram_s1 when CWR_S(7 downto 3) = "00001" else
						  Data_out_sram_s2 when CWR_S(7 downto 3) = "00010" else	
						  Data_out_sram_s3 when CWR_S(7 downto 3) = "00100" else
						  Data_out_sram_s4 when CWR_S(7 downto 3) = "01000" else
						  Data_out_sram_s5 when CWR_S(7 downto 3) = "10000" else
						  (others => '0');



PCI_BUS <= x"0000" & data_out_sram when  (dtr = '0' and den = '0'  and address(15 downto 0) = x"000C") else
		 	 (others => 'Z');


--================================ CONTROL SIGNALS FOR SRAM 1 =======================================

--CS_SRAM1 <= CS_BAR_S when CWR_S(7 downto 3) = "00001" else
--		  '1';	

--WR_SRAM1 <= WR_SRAM_S when CWR_S(7 downto 3) = "00001" else
--		  '1';

--OE_SRAM1 <= OE_SRAM_S when CWR_S(7 downto 3) = "00001" else
--		  '1';

	
--CS_SRAM2 <= CS_BAR_S when CWR_S(6 downto 3) = "0010" else
--		  '1';	

--CS_SRAM3 <= CS_BAR_S when CWR_S(6 downto 3) = "0100" else
--		  '1';	

--CS_SRAM4 <= CS_BAR_S when CWR_S(6 downto 3) = "1000" else
--		  '1';	

END Behavioral;