sram_interface.vhd

The Hardware folder contains the following files:- 1) Sram_Interface.bit -----------------> Bi

--=======================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--=======================================================================================
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

--=======================================================================================
entity Sram_Interface is
    Port (
		 pci_clk	 	: in std_logic;
       pci_reset 	: in std_logic;
    	 lhold 	: in std_logic;
     	 lholda 	: out std_logic;
       lint 	: out std_logic;
		 pci_bus 	: inout std_logic_vector(31 downto 0);
		 dtr		: in std_logic;
		 den		: in std_logic;
		 ads		: in std_logic;
		 ccs		: out std_logic;	


------------------------SRAM INTERFACING SIGNALS-----------------------------------------

--==================================SRAM 1==========================================================		

		Address_SRAM1 	: out std_logic_vector(19 downto 0);
		Data_SRAM1 		: inout std_logic_vector(15 downto 0);					 
		WE_SRAM1    	: out std_logic;
		OE_SRAM1    	: out std_logic;
		CS_SRAM1    	: out std_logic;		

--==================================SRAM 2==========================================================		

		Address_SRAM2 	: out std_logic_vector(19 downto 0);
		Data_SRAM2 		: inout std_logic_vector(15 downto 0);					 
		WE_SRAM2    	: out std_logic;
		OE_SRAM2    	: out std_logic;
		CS_SRAM2    	: out std_logic;		

--==================================SRAM 3==========================================================		

		Address_SRAM3 	: out std_logic_vector(19 downto 0);
		Data_SRAM3 		: inout std_logic_vector(15 downto 0);					 
		WE_SRAM3    	: out std_logic;
		OE_SRAM3    	: out std_logic;
		CS_SRAM3    	: out std_logic;		

--==================================SRAM 4==========================================================		

		Address_SRAM4 	: out std_logic_vector(19 downto 0);
		Data_SRAM4 		: inout std_logic_vector(15 downto 0);					 
		WE_SRAM4    	: out std_logic;
		OE_SRAM4    	: out std_logic;
		CS_SRAM4    	: out std_logic;		

--==================================SRAM 5==========================================================		

		Address_SRAM5 	: out std_logic_vector(19 downto 0);
		Data_SRAM5 		: inout std_logic_vector(15 downto 0);					 
		WE_SRAM5    	: out std_logic;
		OE_SRAM5    	: out std_logic;
		CS_SRAM5    	: out std_logic		

------------------------------------------------------------------------------------------				 				 
		);
end Sram_Interface;

--=======================================================================================
architecture Behavioral of Sram_Interface is
--=======================================================================================

	COMPONENT sram_rd_wr
	PORT(
		rst : IN std_logic;
		clk : IN std_logic;
		init		: in std_logic;
		read_writebar : IN std_logic;
		data_in : IN std_logic_vector(15 downto 0);
		data_ready_in : IN std_logic;    
		addr_load	: in std_logic ;
		Address_SRAM_in : in std_logic_vector(19 downto 0); --
		data_sram : INOUT std_logic_vector(15 downto 0);      
		Address_SRAM : out 	std_logic_vector(19 downto 0);
		cs_bar_sram : OUT std_logic;
		wr_bar_sram : OUT std_logic;
		oe_bar_sram : OUT std_logic;
		send_data_sram_ctrl	: in 	std_logic;	
		data_out 	  : OUT std_logic_vector(15 downto 0);
		data_en_out : OUT std_logic
		);
	END COMPONENT;

--=======================================================================================
	signal reset_s 	: std_logic;
	signal address 	: std_logic_vector(31 downto 0);
	signal address_in 	: std_logic_vector(31 downto 0);
	signal data_s  	: std_logic_vector(31 downto 0);
	signal CWR_S  		: std_logic_vector(31 downto 0);
	signal data_in_sram 	 : std_logic_vector(15 downto 0);
	
	signal data_out_sram 	: std_logic_vector(15 downto 0);
	
	signal data_out_sram_s1, data_out_sram_s2, data_out_sram_s3,data_out_sram_s4,
			 data_out_sram_s5   : std_logic_vector(15 downto 0);

	signal Address_sram_in :  std_logic_vector(19 downto 0);

	signal address_load : std_logic;

	signal init1, init2, init3, init4, init5 : std_logic;

	SIGNAL den_in, Read_Write,  den_out1, den_out2, den_out3, den_out4, den_out5,
			 send_en_rd	: std_logic;
	
	type state is (start, dly, En_gen, stop);
	signal ps, ns : state ;

	type state1 is (start1, dly1, En_gen1, stop1);
	signal p_s, n_s : state1 ;

	type state2 is (start2, dly2, addr_en);
	signal ps1, ns1 : state2;


--=======================================================================================		
begin
--======================================================================================
	
	reset_s <= (not pci_reset);

	lholda <= lhold;
	lint <= '1';
	ccs <= '1';


--===============================COMPONENT INSTANTIATION SRAM 1 ==============================

	Sram1: sram_rd_wr PORT MAP(
		rst => reset_s ,
		clk => pci_clk,
		init => init1,
		read_writebar => Read_Write,
		data_sram => Data_SRAM1,	  --entity
		Address_SRAM_in => Address_SRAM_in,
		addr_load => address_load,

		Address_SRAM => Address_SRAM1,	--entity
		cs_bar_sram => CS_SRAM1,		  --entity
		wr_bar_sram => WE_SRAM1,		  --entity
		oe_bar_sram => OE_SRAM1,		  --entity
		data_in => data_in_sram,
		data_out => data_out_sram_s1,
		send_data_sram_ctrl	=> send_en_rd,
		data_en_out => den_out1,
		data_ready_in => den_in
	);

--======================================================================================

--===============================COMPONENT INSTANTIATION SRAM 2 ==============================


Sram2: sram_rd_wr PORT MAP(
		rst => reset_s ,
		clk => pci_clk,
		init => init2,
		read_writebar => Read_Write,
		data_sram => Data_SRAM2,	  --entity
		Address_SRAM_in => Address_SRAM_in,
		addr_load => address_load,

		Address_SRAM => Address_SRAM2,	--entity
		cs_bar_sram => CS_SRAM2,		  --entity
		wr_bar_sram => WE_SRAM2,		  --entity
		oe_bar_sram => OE_SRAM2,		  --entity
		data_in => data_in_sram,
		data_out => data_out_sram_s2,
		send_data_sram_ctrl	=> send_en_rd,
		data_en_out => den_out2,
		data_ready_in => den_in
	);


--===============================COMPONENT INSTANTIATION SRAM 3 ==============================

	Sram3: sram_rd_wr PORT MAP(
		rst => reset_s ,
		clk => pci_clk,
		init => init3,
		read_writebar => Read_Write,
		data_sram => Data_SRAM3,	  --entity
		Address_SRAM_in => Address_SRAM_in,
		addr_load => address_load,

		Address_SRAM => Address_SRAM3,	--entity
		cs_bar_sram => CS_SRAM3,		  --entity
		wr_bar_sram => WE_SRAM3,		  --entity
		oe_bar_sram => OE_SRAM3,		  --entity
		data_in => data_in_sram,
		data_out => data_out_sram_s3,
		send_data_sram_ctrl	=> send_en_rd,
		data_en_out => den_out3,
		data_ready_in => den_in
	);

--======================================================================================

--===============================COMPONENT INSTANTIATION SRAM 4 ==============================


Sram4: sram_rd_wr PORT MAP(
		rst => reset_s ,
		clk => pci_clk,
		init => init4,
		read_writebar => Read_Write,
		data_sram => Data_SRAM4,	  --entity
		Address_SRAM_in => Address_SRAM_in,
		addr_load => address_load,

		Address_SRAM => Address_SRAM4,	--entity
		cs_bar_sram => CS_SRAM4,		  --entity
		wr_bar_sram => WE_SRAM4,		  --entity
		oe_bar_sram => OE_SRAM4,		  --entity
		data_in => data_in_sram,
		data_out => data_out_sram_s4,
		send_data_sram_ctrl	=> send_en_rd,
		data_en_out => den_out4,
		data_ready_in => den_in
	);


--===============================COMPONENT INSTANTIATION SRAM 5 ==============================


Sram5: sram_rd_wr PORT MAP(
		rst => reset_s ,
		clk => pci_clk,
		init => init5,
		read_writebar => Read_Write,
		data_sram => Data_SRAM5,	  --entity
		Address_SRAM_in => Address_SRAM_in,
		addr_load => address_load,

		Address_SRAM => Address_SRAM5,	--entity
		cs_bar_sram => CS_SRAM5,		  --entity
		wr_bar_sram => WE_SRAM5,		  --entity
		oe_bar_sram => OE_SRAM5,		  --entity
		data_in => data_in_sram,
		data_out => data_out_sram_s5,
		send_data_sram_ctrl	=> send_en_rd,
		data_en_out => den_out5,
		data_ready_in => den_in
	);

--===============================================================================================


process (pci_clk,reset_s,ads)
begin
	if(reset_s = '1') then
		address <= (others => '0');
	elsif(pci_clk'event and pci_clk = '1') then
		if(ads = '0') then
			address <= pci_bus;
		end if;
	end if;
end process;

--=======================LATCHING THE CONTROL WORD FOR FPGA==============================

process (pci_clk,reset_s,dtr, den, address, pci_bus)
begin
	if(reset_s = '1'  ) then 
	 CWR_S <= (others => '0');
	elsif(pci_clk'event and pci_clk = '1') then
		if(dtr = '1' and den = '0' and address(15 downto 0) = x"0000") then
			CWR_S <= Pci_bus;
		end if;
	end if;
end process;