sram_interface_tb.vhd

The Hardware folder contains the following files:- 1) Sram_Interface.bit -----------------> Bi

-- VHDL Test Bench Created from source file sram_interface.vhd -- 20:07:08 08/18/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY sram_interface_tb IS
END sram_interface_tb;

ARCHITECTURE behavior OF sram_interface_tb IS 

	COMPONENT sram_interface
	PORT(
		pci_clk : IN std_logic;
		pci_reset : IN std_logic;
		lhold : IN std_logic;
		dtr : IN std_logic;
		den : IN std_logic;
		ads : IN std_logic;    
		pci_bus : INOUT std_logic_vector(31 downto 0);
		Data_SRAM1 : INOUT std_logic_vector(15 downto 0);      
		lholda : OUT std_logic;
		lint : OUT std_logic;
		ccs : OUT std_logic;
		Address_SRAM1 : OUT std_logic_vector(19 downto 0);
		WE_SRAM1 : OUT std_logic;
		OE_SRAM1 : OUT std_logic;
		CS_SRAM1 : OUT std_logic
		);
	END COMPONENT;

	SIGNAL pci_clk :  std_logic:= '0';
	SIGNAL pci_reset :  std_logic:= '0';
	SIGNAL lhold :  std_logic:= '1' ;
	SIGNAL lholda :  std_logic;
	SIGNAL lint :  std_logic:= '1';
	SIGNAL pci_bus :  std_logic_vector(31 downto 0):= (others => 'Z');
	SIGNAL dtr :  std_logic:= '1';
	SIGNAL den :  std_logic:= '1';
	SIGNAL ads :  std_logic:= '1';
	SIGNAL ccs :  std_logic:= '1';
	SIGNAL Address_SRAM1 :  std_logic_vector(19 downto 0);
	SIGNAL Data_SRAM1 :  std_logic_vector(15 downto 0):= (others => 'Z');
	SIGNAL WE_SRAM1 :  std_logic;
	SIGNAL OE_SRAM1 :  std_logic;
	SIGNAL CS_SRAM1 :  std_logic;

BEGIN

	uut: sram_interface PORT MAP(
		pci_clk => pci_clk,
		pci_reset => pci_reset,
		lhold => lhold,
		lholda => lholda,
		lint => lint,
		pci_bus => pci_bus,
		dtr => dtr,
		den => den,
		ads => ads,
		ccs => ccs,
		Address_SRAM1 => Address_SRAM1,
		Data_SRAM1 => Data_SRAM1,
		WE_SRAM1 => WE_SRAM1,
		OE_SRAM1 => OE_SRAM1,
		CS_SRAM1 => CS_SRAM1
	);


-- *** Test Bench - User Defined Section ***
	pci_clk <= not pci_clk after 30 ns;
	
	pci_reset <= '1' after 105 ns ;
	
	ads <= '0' after 210 ns, '1' after 270 ns, 
		  '0' after 630 ns, '1' after 690 ns,
		  '0' after 930 ns, '1' after 990 ns,
		  '0' after 1830 ns , '1' after 1890 ns ,
		  '0' after 2790 ns , '1' after 2850 ns,
--		  '0' after 3030 ns , '1' after 3090 ns,
		  '0' after 4050 ns , '1' after 4110 ns,
		  '0' after 5370 ns , '1' after 5430 ns ;	  

	den <= '0' after 270 ns, '1' after 330 ns,
		  '0' after 690 ns, '1' after 750 ns,
		  '0' after 990 ns, '1' after 1050 ns,
		  '0' after 1890 ns, '1' after 1950 ns,
		  '0' after 2850 ns , '1' after 2910 ns,
--		  '0' after 3090 ns , '1' after 3150 ns,
		  '0' after 4110 ns , '1' after 4170 ns,
		  '0' after 5430 ns , '1' after 5490 ns;
	
	dtr <=  '1', --'0' after 3090 ns , '1' after 3150 ns,
		  '0' after 4110 ns , '1' after 4170 ns,
		  '0' after 5430 ns , '1' after 5490 ns;

		--'0' after 270 ns, '1' after 330 ns,
		 -- '0' after 690 ns, '1' after 750 ns,
		 -- '0' after 990 ns, '1' after 1050 ns ;
	 
	Data_SRAM1 <= x"3031" after 4230 ns, (others => 'Z') after 4470 ns ; 	

	pci_bus <= x"00000000" after 210 ns, x"00000008" after 270 ns, (others => 'Z') after 330 ns,
			 x"00000004" after 630 ns, x"00000000" after 690 ns, (others => 'Z') after 750 ns,
			 x"00000008" after 930 ns, x"00003031" after 990 ns, (others => 'Z') after 1050 ns,

			 x"00000000" after 1830 ns, x"0000000C" after 1890 ns, (others => 'Z') after 1950 ns, 
			 x"00000004" after 2790 ns, x"00000000" after 2850 ns, (others => 'Z') after 2910 ns,
			 x"0000000c" after 4050 ns ,(others => 'Z')after 4110 ns ,
			 x"0000000c" after 5370 ns ,(others => 'Z')after 5430 ns ;

-- *** End Test Bench - User Defined Section ***

END;