📄 jpeginit.asm
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[!A1] B .S1 L13 ; |168|
[ A1] MVK .S1 0x1,A5 ; |168|
[ A1] ADD .L1X B0,A0,A7
NOP 3
; BRANCH OCCURS ; |168|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 168
;* Loop opening brace source line : 169
;* Loop closing brace source line : 174
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 25
;* Unpartitioned Resource Bound : 5
;* Partitioned Resource Bound(*) : 6
;* Resource Partition:
;* A-side B-side
;* .L units 0 1
;* .S units 1 1
;* .D units 3 2
;* .M units 1 1
;* .X cross paths 0 2
;* .T address paths 3 2
;* Long read paths 1 1
;* Long write paths 0 0
;* Logical ops (.LS) 0 1 (.L or .S unit)
;* Addition ops (.LSD) 12 5 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 2
;* Bound(.L .S .D .LS .LSD) 6* 4
;*
;* Searching for software pipeline schedule at ...
;* ii = 25 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 10/7
;* Max Cond Regs Live : 3/1
;* ii = 25 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/8
;* Max Cond Regs Live : 3/1
;* ii = 25 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/7
;* Max Cond Regs Live : 3/1
;* ii = 26 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 10/7
;* Max Cond Regs Live : 3/1
;* ii = 26 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/8
;* Max Cond Regs Live : 3/1
;* ii = 26 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/7
;* Max Cond Regs Live : 3/1
;* ii = 27 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 10/7
;* Max Cond Regs Live : 3/1
;* ii = 27 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/8
;* Max Cond Regs Live : 3/1
;* ii = 27 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/7
;* Max Cond Regs Live : 3/1
;* ii = 28 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 10/7
;* Max Cond Regs Live : 3/1
;* ii = 28 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/8
;* Max Cond Regs Live : 3/1
;* ii = 28 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/7
;* Max Cond Regs Live : 3/1
;* ii = 29 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 10/7
;* Max Cond Regs Live : 3/1
;* ii = 29 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/8
;* Max Cond Regs Live : 3/1
;* ii = 29 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/7
;* Max Cond Regs Live : 3/1
;* ii = 30 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 10/7
;* Max Cond Regs Live : 3/1
;* ii = 30 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/8
;* Max Cond Regs Live : 3/1
;* ii = 30 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/7
;* Max Cond Regs Live : 3/1
;* ii = 31 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/8
;* Max Cond Regs Live : 3/1
;* ii = 31 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/8
;* Max Cond Regs Live : 3/1
;* ii = 31 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/7
;* Max Cond Regs Live : 3/1
;* ii = 32 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/8
;* Max Cond Regs Live : 3/1
;* ii = 32 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/8
;* Max Cond Regs Live : 3/1
;* ii = 32 Too many predicates live on one side
;* Regs Live Always : 4/3 (A/B-side)
;* Max Regs Live : 11/7
;* Max Cond Regs Live : 3/1
;* Disqualified loop: Did not find schedule
;*
;* To improve performance on this loop, try option -mh14
;*----------------------------------------------------------------------------*
L12:
.line 12
LDBU .D1T1 *A7,A8 ; |170|
NOP 4
MPYSU .M2X 6,A8,B5 ; |170|
NOP 1
ADD .S2X A6,B5,B5 ; |170|
STH .D2T2 B4,*B5 ; |170|
.line 13
LDBU .D1T1 *A7++,A8 ; |171|
NOP 4
MPYSU .M1 6,A8,A8 ; |171|
NOP 1
ADD .D1 A6,A8,A8 ; |171|
STB .D1T1 A3,*+A8(2) ; |171|
.line 14
ADD .D2 1,B0,B0 ; |172|
.line 15
ADD .D2 1,B4,B4 ; |173|
EXTU .S2 B4,16,16,B4 ; |173|
.line 16
LDBU .D1T1 *+A3[A4],A8 ; |174|
ADD .D1 1,A5,A5 ; |174|
NOP 3
CMPLT .L1 A8,A5,A1 ; |174|
[!A1] B .S1 L12 ; |174|
NOP 5
; BRANCH OCCURS ; |174|
;** --------------------------------------------------------------------------*
L13:
.line 17
EXTU .S2 B4,17,16,B4 ; |175|
.line 18
SUB .D2 B1,1,B1 ; |176|
[ B1] B .S1 L11 ; |176|
ADD .D1 1,A3,A3 ; |176|
NOP 4
; BRANCH OCCURS ; |176|
;** --------------------------------------------------------------------------*
.line 20
CMPGT .L2 B0,0,B1 ; |178|
[!B1] B .S1 L17 ; |178|
[ B1] ADD .S2X 4,A6,B4
NOP 4
; BRANCH OCCURS ; |178|
;** --------------------------------------------------------------------------*
.line 22
MVC .S2 CSR,B6
AND .S2 -2,B6,B5
MVC .S2 B5,CSR ; interrupts off
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 178
;* Loop opening brace source line : 179
;* Loop closing brace source line : 181
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 7
;* Unpartitioned Resource Bound : 1
;* Partitioned Resource Bound(*) : 1
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 1* 0
;* .D units 1* 1*
;* .M units 0 0
;* .X cross paths 0 1*
;* .T address paths 1* 1*
;* Long read paths 0 1*
;* Long write paths 0 0
;* Logical ops (.LS) 0 1 (.L or .S unit)
;* Addition ops (.LSD) 0 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1* 1*
;* Bound(.L .S .D .LS .LSD) 1* 1*
;*
;* Searching for software pipeline schedule at ...
;* ii = 7 Schedule found with 1 iterations in parallel
;* Done
;*
;* Collapsed epilog stages : 0
;* Collapsed prolog stages : 0
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
L14: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L15: ; PIPED LOOP KERNEL
[ B0] SUB .D2 B0,1,B0 ; |181| <0,0>
|| LDBU .D1T1 *A0++,A3 ; |180| <0,0> ^
[ B0] B .S1 L15 ; |181| <0,1>
NOP 3
MV .S2X A3,B5 ; |180| <0,5> ^ Define a twin register
STH .D2T2 B5,*B4++(6) ; |180| <0,6> ^
;** --------------------------------------------------------------------------*
L16: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
MVC .S2 B6,CSR ; interrupts on
;** --------------------------------------------------------------------------*
L17:
.line 25
RET .S2 B3 ; |183|
NOP 5
; BRANCH OCCURS ; |183|
.endfunc 183,000000000h,0
;******************************************************************************
;* MARK THE END OF THE SCALAR INIT RECORD IN CINIT:C *
;******************************************************************************
CIR: .sect ".cinit:c"
;******************************************************************************
;* UNDEFINED EXTERNAL REFERENCES *
;******************************************************************************
.global _pVLITAB
;******************************************************************************
;* TYPE INFORMATION *
;******************************************************************************
.sym _BYTE, 0, 12, 13, 8
.sym _WORD, 0, 13, 13, 16
.stag _tagHUFFCODE, 48
.member _code, 0, 13, 8, 16
.member _length, 16, 12, 8, 8
.member _val, 32, 13, 8, 16
.eos
.sym _HUFFCODE, 0, 8, 13, 48,_tagHUFFCODE
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