ddc.m

This lab exercise will introduce you to the AccelWare IP generators. AccelWare is a library of over

%       AccelDSP 8.1.1 build 690 Production, compiled Apr 26 2006 
% 
%    THIS IS UNPUBLISHED, LICENSED SOFTWARE THAT IS THE CONFIDENTIAL 
%        AND PROPRIETARY PROPERTY OF XILINX OR ITS LICENSORS 
% 
%     Copyright(c) Xilinx, Inc., 2000-2006, All Rights Reserved. 
%     Reproduction or reuse, in any form, without the explicit written 
%     consent of Xilinx, Inc., is strictly prohibited. 

function [y,valid,Sine] = ddc(x,PhaseIn)

% Create Direct Digital Synthesizer
persistent phase_accum
if isempty(phase_accum)
   phase_accum = 0;
end
theta = floor(phase_accum/2^11)*pi/2^8;
phase_accum = phase_accum + PhaseIn;
Sine = sin(theta);

% Add the DDS output to the input signal
x_sum = x*Sine;

% polyphase decimation by 2 filter
[y1,valid1] = firdecim_001(x_sum);

if valid1 == 1
    [y,valid] = firdecim_002(y1);
else
    y = 0;
    valid = 0;
end