fir_compare.acc

This getting started exercise will guide you through the step-by-step process of transforming a MATL

#       AccelDSP 8.1.1 build 690 Production, compiled Apr 26 2006 
# 
#    THIS IS UNPUBLISHED, LICENSED SOFTWARE THAT IS THE CONFIDENTIAL 
#        AND PROPRIETARY PROPERTY OF XILINX OR ITS LICENSORS 
# 
#     Copyright(c) Xilinx, Inc., 2000-2006, All Rights Reserved. 
#     Reproduction or reuse, in any form, without the explicit written 
#     consent of Xilinx, Inc., is strictly prohibited. 
SetProjectOption -dc_synthetic_library {dw_foundation.sldb dw01.sldb dw02.sldb}
SetProjectOption -default_overflow_mode wrap
SetProjectOption -default_round_mode floor
SetProjectOption -device XC4VSX25
SetProjectOption -directivesfile fir_compare.add
SetProjectOption -dontcare_value 0
SetProjectOption -enableiohandshake 0
SetProjectOption -fi_objects 0
SetProjectOption -fixedpointlanguage C++
SetProjectOption -frequency 10
SetProjectOption -impltool ISE
SetProjectOption -message_level_info {1 1}
SetProjectOption -message_level_warn {1 1}
SetProjectOption -package FF668
SetProjectOption -pnr_effort High
SetProjectOption -quantizer_max_constant_fractional_length 12
SetProjectOption -replaceconstantmults 1
SetProjectOption -retiming 1
SetProjectOption -scalarize_io 0
SetProjectOption -scriptfile fir_compare_script.m
SetProjectOption -show_overflows 1
SetProjectOption -show_underflows 1
SetProjectOption -signal_name_clock Clock
SetProjectOption -signal_name_input_available ac_InputAvail
SetProjectOption -signal_name_input_request ac_InputReq
SetProjectOption -signal_name_output_acknowledge ac_OutputAck
SetProjectOption -signal_name_output_available ac_OutputAvail
SetProjectOption -signal_name_reset Reset
SetProjectOption -simtool Modelsim
SetProjectOption -speed -12
SetProjectOption -sync_reset 1
SetProjectOption -synth_auto_constrain_io 0
SetProjectOption -synth_enable_io_insertion true
SetProjectOption -synth_fanout_limit 500
SetProjectOption -synth_resource_sharing 1
SetProjectOption -synthtool XST
SetProjectOption -targetlanguage VHDL
SetProjectOption -tb_max_errors 0
SetProjectOption -tb_output_latency 0
SetProjectOption -technology Virtex-4
SetProjectOption -techvendor Xilinx
SetProjectOption -unroll_array_adds 1
SetProjectOption -unroll_array_multiplies 1
SetProjectOption -unroll_array_subtracts 1
SetProjectOption -unroll_for_loops 0
SetProjectOption -unroll_matrix_multiplies 0
SetProjectOption -writeimplconfigfile 0