main.c

Using the ADSP-BF561 Blackfin Processor as a TFT-LCD Controller

/*****************************************************************************
**																			**
**	 Project Name: 	LCD											**	
**																			**
******************************************************************************

(C) Copyright 2005 - Analog Devices, Inc.  All rights reserved.

File Name:		main.c

Date Modified:	5/1/05		CL		Rev 1.0

Software:       VisualDSP++3.5

Hardware:		ADSP-BF561 EZ-KIT Lite

Special Connections:  None

Purpose:		This is the main file that calls all of the initialization
			routines and enables the final DMA/PPI channels.
				
******************************************************************************/



#include "main.h"
#include "..\Shared Memory L2\L2_SRAM.h"
#include "sysreg.h"

#pragma retain_name
int __cplb_ctrl = CPLB_ENABLE_DCACHE | CPLB_ENABLE_DCACHE2 |CPLB_ENABLE_DCPLBS;

volatile short descript_buf_rx[DESCRIPTOR_SIZE*NUM_BUFFERS];
volatile int rx_frame_buffer_addr[NUM_BUFFERS];
volatile int temp_cycle_read;

// User program
void main() {

	volatile int *bufferPtr;
	volatile char loop_forever_a = 1;

		
	bufferPtr = rx_frame_buffer_addr;
	
	// unblock Core B if dual core operation is desired	
#ifndef RUN_ON_SINGLE_CORE
	*pSICA_SYSCR &= 0xFFDF; // clear bit 5 to unlock  
#endif

	Set_PLL( (short)(CORECLK/CLKIN), (short)(CORECLK/SYSCLK));			// sets Core and System Clocks to the values defined in system.h 
	InitSDRAM();
	Reset_ADV7183();
	InitFrameBufPtr(rx_frame_buffer_addr, sizeof(int), NUM_BUFFERS);	
	Init_Interrupts_A();
	
	*pDCPLB_DATA2 &= 0xffffefff;
	*pDCPLB_DATA2 |= 0x00000002;
	ssync();
	
	Init_DMA_A(descript_buf_rx, bufferPtr);
	Init_PPI_A();
	ssync();
	
	*pDMA1_0_CONFIG |= 0x1;
	ssync();
	*pPPI0_CONTROL |= 0x1;
	ssync();
	
	while(loop_forever_a)
		idle();

}