main.c

Using the ADSP-BF561 Blackfin Processor as a TFT-LCD Controller

/*****************************************************************************
**																			**
**	 Project Name: 	LCD											**	
**																			**
******************************************************************************

(C) Copyright 2005 - Analog Devices, Inc.  All rights reserved.

File Name:		main.c

Date Modified:	5/1/05		CL		Rev 1.0

Software:       VisualDSP++3.5

Hardware:		ADSP-BF561 EZ-KIT Lite

Special Connections:  None

Purpose:		This is the main file for Core B, calling all of the 
			other processing routines.  It also does the final 
			enabling of the Timers, DMA, and PPI channels.
				
******************************************************************************/


#include "main.h"
#include "..\Shared Memory L2\L2_SRAM.h"

volatile short descript_buf_tx[DESCRIPTOR_SIZE*NUM_BUFFERS];
volatile int tx_frame_buffer_addr[NUM_BUFFERS];
volatile char j=0;

#pragma retain_name
int __cplb_ctrl = CPLB_ENABLE_DCACHE | CPLB_ENABLE_DCACHE2 |CPLB_ENABLE_DCPLBS;

// User program
void main() {

	char i;
	volatile char loop_forever = 1;
	volatile int *tx_bufferPtr;
	
	tx_bufferPtr = tx_frame_buffer_addr;

	// set Clocks
	Set_PLL( (short)(CORECLK/CLKIN), (short)(CORECLK/SYSCLK));			// sets Core and System Clocks to the values defined in system.h 
	InitFrameBufPtr(tx_frame_buffer_addr, sizeof(int), NUM_BUFFERS);
	Init_Interrupts_B();
	
	*pDCPLB_DATA2 &= 0xffffefff;
	*pDCPLB_DATA2 |= 0x00000002;
	ssync();
	
	Init_PF();	
	Init_DMA(descript_buf_tx, tx_bufferPtr);
	Init_Timers();
	Init_PPI();
	
	while(!ready_signal)
		idle();
		
	Decimate_h(sFrame0, Decimate0_h);
	_YCbCrtoRGB(Decimate0_h, dFrame0, 76800);
	
	if(enable_dma_ppi != 1){
		enable_dma_ppi=1;
		ssync();
		frame_counter = 0;
		ssync();
					
		//Enable DMA.
		*pDMA1_1_CONFIG |= 0x1;
		ssync();
	
		//Enable PPI.
		*pPPI1_CONTROL |= 0x1;
	
		ssync();
		
		//Enable Timer 8:DCLK	
		*pTMRS4_ENABLE = 0x0007;
		ssync();
	
		for(i=0; i<12; i++)
			ssync();
		
		*pTMRS8_ENABLE = 0x00c2;
		ssync();
		
		*pFIO0_FLAG_D |= 0x0100;
		ssync();
		
	}
	
	while(loop_forever==1)
		idle();
				
}		// main