sdram_ initcode.asm

Using the Blackfin Processor SPORT to Emulate a SPI Interface

/********************************************************************/
/*  This file contains 3 sections:																	*/
/*																																	*/
/*	1) A Pre-Init Section - this section saves off all the					*/
/*		registers of the DSP.																					*/
/*																																	*/
/*	2) A Init Code Section - this section is the customer						*/
/*		initialization code which can be modified by the customer.		*/
/*		As an example, an SDRAM initialization code is supplied.			*/
/*																																	*/
/*	3) A Post-Init Section - this section restores all the					*/
/*		register from the stack.																			*/
/*																																	*/
/*	Customers should not modify the Pre-Init and Post-Init Sections.*/
/*	The Init Code Section can be modified for application use.			*/
/********************************************************************/

#include <defBF537.h>
#define           START_OF_SSL_L	     0xFC60		
#define           START_OF_SSL_H	     0x03FF		

.section program;

/*******Pre-Init Section*********************************************/
/*******DO NOT MODIFY************************************************/

[--SP] = ASTAT;			//Save Regs onto stack
	[--SP] = RETS;
	[--SP] = (r7:0);
	[--SP] = (p5:0);
	[--SP] = I0;
	[--SP] = I1;
	[--SP] = I2;
	[--SP] = I3;
	[--SP] = B0;
	[--SP] = B1;
	[--SP] = B2;
	[--SP] = B3;
	[--SP] = M0;
	[--SP] = M1;
	[--SP] = M2;
	[--SP] = M3;
	[--SP] = L0;
	[--SP] = L1;
	[--SP] = L2;
	[--SP] = L3;
/********************************************************************/

/****************************************************************
*							Init Code Section																	*
*			Please insert Initialization code in this section					*
****************************************************************/

/*******SDRAM Setup************/
Setup_SDRAM:
	P0.L = lo(EBIU_SDRRC); 
	P0.H = hi(EBIU_SDRRC); 		//SDRAM Refresh Rate Control Register
	R0 = 0x03A0(Z); 			 					
	W[P0] = R0;							
	SSYNC;	

	P0.L = lo(EBIU_SDBCTL); 			
	P0.H = hi(EBIU_SDBCTL); 	//SDRAM Memory Bank Control Register
	r0 = 0x25(z);   
	[P0] = R0;
	SSYNC;		

	P0.L = lo(EBIU_SDGCTL); 			
	P0.H = hi(EBIU_SDGCTL);		//SDRAM Memory Global Control Register
	R0.L = 0x998D;
	R0.H = 0x0091;
	[P0] = R0;
	SSYNC;	
/******************************/

/*******SSL execution Setup**********/
    p0.h = hi(EVT1);
    p0.l = lo(EVT1);
    r0.h = START_OF_SSL_H;  
    r0.l = START_OF_SSL_L;  
    [p0] = r0;
    ssync;
/************************************/

/*******************************************************************************/
/*                                                                             */
/*  Initialize Phase Lock Loop for MAX SPORT speed 							   */
/*                                                                             */
/*******************************************************************************/
	R3 = 0x0001(Z);							
	W[P1 + LO(SIC_IWR)]   = R3;				
	
	R3.L = 0x1C00;							// CCLK = 350Mhz   SCLK = 70Mhz			 
	W[P1 + LO(PLL_CTL)]   = R3;				
  	
	SSYNC;
	
	IDLE;
	
/*******Post-Init Section********************************************/
/*******DO NOT MODIFY************************************************/
	L3 = [SP++];		//Restore Regs from Stack
	L2 = [SP++];	
	L1 = [SP++];
	L0 = [SP++];
	M3 = [SP++];
	M2 = [SP++];
	M1 = [SP++];
	M0 = [SP++];
	B3 = [SP++];
	B2 = [SP++];
	B1 = [SP++];
	B0 = [SP++];
	I3 = [SP++];
	I2 = [SP++];
	I1 = [SP++];
	I0 = [SP++];
	(p5:0) = [SP++];  		
	(r7:0) = [SP++];
	RETS = [SP++];
	ASTAT = [SP++];
/********************************************************************/

	RTS;